KSZ8893FQL-FX Micrel Inc, KSZ8893FQL-FX Datasheet - Page 50

2+1 Port 10/100 Switch W/Tranceivers & Frame Buffers, ( )

KSZ8893FQL-FX

Manufacturer Part Number
KSZ8893FQL-FX
Description
2+1 Port 10/100 Switch W/Tranceivers & Frame Buffers, ( )
Manufacturer
Micrel Inc
Datasheet

Specifications of KSZ8893FQL-FX

Controller Type
Ethernet Switch Controller
Interface
MII, RMII, SNI
Voltage - Supply
3.1 V ~ 3.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
128-MQFP, 128-PQFP
Number Of Primary Switch Ports
3
Internal Memory Buffer Size
32
Operating Supply Voltage (typ)
3.3V
Fiber Support
Yes
Integrated Led Drivers
Yes
Power Supply Type
Analog/Digital
Package Type
PQFP
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Temperature Classification
Commercial
Data Rate
1000Mbps
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
576-1603 - EVAL KIT EXPERIMENTAL KSZ8893MQL
Current - Supply
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
576-3273

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
KSZ8893FQL-FX
Manufacturer:
Micrel Inc
Quantity:
1 950
Part Number:
KSZ8893FQL-FX
Manufacturer:
FSC
Quantity:
1 800
Part Number:
KSZ8893FQL-FX
Manufacturer:
Micrel Inc
Quantity:
10 000
Micrel, Inc.
Note: The “Start Switch” bit cannot be set to ‘0’ to stop the switch after a ‘1’ is written to this bit. Thus, it is
recommended that all switch configuration settings are programmed before the “Start Switch” bit is set to ‘1’.
Some of the configuration settings, such as “Aging enable”, “Auto Negotiation Enable”, “Force Speed” and “Power
down” can be programmed after the switch has been started.
The following four figures illustrate the SPI data cycles for “Write”, “Read”, “Multiple Write” and “Multiple Read”. The
read data is registered out of SPIQ on the falling edge of SPIC, and the data input on SPID is registered on the rising
edge of SPIC.
October 2007
Figure 11. SPI Write Data Cycle
Figure 12. SPI Read Data Cycle
50
M9999-101607-1.3
KSZ8893FQL

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