KSZ8893FQL-FX Micrel Inc, KSZ8893FQL-FX Datasheet - Page 2

• Manufacturer Part Number: KSZ8893FQL-FX
• Description: 2+1 Port 10/100 Switch W/Tranceivers & Frame Buffers, ( )
• Manufacturer: Micrel Inc

Specifications of KSZ8893FQL-FX

• Controller Type: Ethernet Switch Controller
• Interface: MII, RMII, SNI
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Data Rate: 1000Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1603 - EVAL KIT EXPERIMENTAL KSZ8893MQL
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-3273

Micrel, Inc.
Features
Integrated 3-Port 10/100 Ethernet Switch
• Three MACs and two PHYs fully compliant with IEEE
• Non-blocking switch fabric assures fast packet
• Full duplex IEEE 802.3x flow control (PAUSE) with
• Half-duplex back pressure flow control
• HP Auto MDI-X for reliable detection of and correction
• Micrel LinkMD
• 100Base-FX, 100Base-SX and 10Base-FL fiber
• MII interface supports both MAC mode and PHY mode
• RMII interface support with external 50MHz system
• 7-wire serial network interface (SNI) support for legacy
• Comprehensive LED Indicator support for link, activity,
Fiber Support
• Integrated LED driver and post amplifier for 10Base-
TTC TS-1000 OAM
• Supports OAM sub-layer which conforms to TS-1000
• Sends and receives OAM frames to Center or
• Loop back mode to support loop back packet from
• Far-end fault detection with disable and enable
• Link Transparency to indicate link down from link
• Unique User Defined Register (UDR) feature brings
Comprehensive Configuration Register Access
• SMI, SPI and I
• MII management (MIIM) interface to PHY registers
• I/O pins strapping and EEPROM to program selective
October 2007
802.3u standard
delivery by utilizing an 1K MAC address lookup table
and a store-and-forward architecture
force mode option
for straight-through and crossover cables with disable
and enable option
identification of faulty copper cabling
support on port 1
clock
MAC
full/half duplex and 10/100 speed
FL and 100Base-SX optical modules
V2 specification from TTC (Telecommunication
Technology Committee)
Terminal side
Center side to Terminal side
partner
OAM to low cost/complexity nodes
internal registers
registers in unmanaged switch mode
®
2
C management interfaces to all 8-bit
TDR-based cable diagnostics permit
2
• Control registers configurable on the fly (port-priority,
QoS/CoS Packet Prioritization Support
• Per port, 802.1p and DiffServ-based
• Re-mapping of 802.1p priority field per port basis
• Four priority levels
Advanced Switch Features
• IEEE 802.1q VLAN support for up to 16 groups (full-
• VLAN ID tag/untag options, per port basis
• IEEE 802.1p/q tag insertion or removal on a per port
• Programmable rate limiting at the ingress and egress
• Broadcast storm protection with % control (global and
• IEEE 802.1d spanning tree protocol support
• Special tagging mode to inform the processor which
• IGMP snooping (Ipv4) and MLD snooping (Ipv6)
• MAC filtering function to forward unknown unicast
• Double-tagging support
Low Latency Support
• Repeater mode
Switch Monitoring Features
• Port mirroring/monitoring/sniffing: ingress and/or
• MIB counters for fully compliant statistics gathering, 34
• Loopback modes for remote diagnostic of failure
Low Power Dissipation
• Full-chip hardware power-down (register configuration
• Per port based software power-save on PHY (idle link
• Voltages:
Available in 128-Pin PQFP, Lead-free package
802.1p/d/q, AN…)
range of VLAN IDs)
basis (egress)
on a per port basis
per port basis)
ingress port receives the packet
support for multicast packet filtering
packets to specified port
egress traffic to any port or MII
MIB counters per port
not saved)
detection, register configuration preserved)
– Core 1.2V
– I/O and Transceiver 3.3V
M9999-101607-1.3
KSZ8893FQL