KSZ8893FQL-FX Micrel Inc, KSZ8893FQL-FX Datasheet - Page 47

• Manufacturer Part Number: KSZ8893FQL-FX
• Description: 2+1 Port 10/100 Switch W/Tranceivers & Frame Buffers, ( )
• Manufacturer: Micrel Inc

Specifications of KSZ8893FQL-FX

• Controller Type: Ethernet Switch Controller
• Interface: MII, RMII, SNI
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Data Rate: 1000Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1603 - EVAL KIT EXPERIMENTAL KSZ8893MQL
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-3273

Micrel, Inc.
KSZ8893FQL
DiffServ-Based Priority
DiffServ-based priority uses the ToS registers (registers 96 to 111) in the Advanced Control Registers section. The ToS
priority control registers implement a fully decoded, 64-bit Differentiated Services Code Point (DSCP) register to
determine packet priority from the 6-bit ToS field in the IP header. When the most significant 6 bits of the ToS field are
fully decoded, the resultant of the 64 possibilities is compared with the corresponding bits in the DSCP register to
determine priority.
Rate Limiting Support
The KSZ8893FQL supports hardware rate limiting from 64 Kbps to 88 Mbps, independently on the “receive side” and
on the “transmit side” on a per port basis. For 10Base-T, a rate setting above 10 Mbps means the rate is not limited. On
the receive side, the data receive rate for each priority at each port can be limited by setting up Ingress Rate Control
Registers. On the transmit side, the data transmit rate for each priority queue at each port can be limited by setting up
Egress Rate Control Registers. The size of each frame has options to include minimum IFG (Inter Frame Gap) or
Preamble byte, in addition to the data field (from packet DA to FCS).
For ingress rate limiting, KSZ8893FQL provides options to selectively choose frames from all types, multicast,
broadcast, and flooded unicast frames. The KSZ8893FQL counts the data rate from those selected type of frames.
Packets are dropped at the ingress port when the data rate exceeds the specified rate limit.
For egress rate limiting, the Leaky Bucket algorithm is applied to each output priority queue for shaping output traffic.
Inter frame gap is stretched on a per frame base to generate smooth, non-burst egress traffic. The throughput of each
output priority queue is limited by the egress rate specified.
If any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in the
output queue and packet memory. After the memory of the queue or the port is used up, packet dropping or flow control
will be triggered. As a result of congestion, the actual egress rate may be dominated by flow control/dropping at the
ingress end, and may be therefore, slightly less than the specified egress rate.
To reduce congestion, it is a good practice to make sure the egress bandwidth exceeds the ingress bandwidth.
Unicast MAC Address Filtering
The unicast MAC address filtering function works in conjunction with the static MAC address table. First, the static MAC
address table is used to assign a dedicated MAC address to a specific port. If a unicast MAC address is not recorded in
the static table, it is also not learned in the dynamic MAC table. The KSZ8893FQL is then configured with the option to
either filter or forward unicast packets for an unknown MAC address. This option is enabled and configured in register
14.
This function is useful in preventing the broadcast of unicast packets that could degrade the quality of the port in
applications such as voice over Internet Protocol (VoIP).
Configuration Interface
The KSZ8893FQL can operate as both a managed switch and an unmanaged switch.
In unmanaged mode, the KSZ8893FQL is typically programmed using an EEPROM. If no EEPROM is present, the
KSZ8893FQL is configured using its default register settings. Some default settings are configured via strap-in pin
options. The strap-in pins are indicated in the “KSZ8893FQL Pin Description and I/O Assignment” table.
I2C Master Serial Bus Configuration
2
With an additional I
C (“2-wire”) EEPROM, the KSZ8893FQL can perform more advanced switch features like
“broadcast storm protection” and “rate control” without the need of an external processor.
2
For KSZ8893FQL I
C Master configuration, the EEPROM stores the configuration data for register 0 to register 120 (as
defined in the KSZ8893FQL register map) with the exception of the “Read Only” status registers. After the de-assertion
of reset, the KSZ8893FQL sequentially reads in the configuration data for all 121 registers, starting from register 0. The
configuration access time (t
) is less than 15 ms, as depicted in the following figure.
prgm
47
October 2007
M9999-101607-1.3