DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 11

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

2
2.1 General
2.2 Microprocessor Interface
2.3 Link Aggregation (Inverse Multiplexing)
2.4 HDLC Ethernet Mapping
2.5 X.86 (Link Access Protocol for SONET/SDH) Ethernet Mapping
FEATURE HIGHLIGHTS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
400-pin, 27mm BGA package
1.8V and 3.3V supplies
IEEE 1149.1 JTAG boundary scan
Software access to device ID and silicon revision
Development support includes evaluation kit, driver source code, and reference designs
Programmable output clocks for fractional T1, E1, H0, and H12 applications
Parallel control port with 8-bit data bus
Nonmultiplexed Intel and Motorola timing modes
Internal software reset and external hardware reset input pin
Supports polled or interrupt-driven environments
Software access to device ID and silicon revision
Global interrupt output pin
Link aggregation for up to four T1/E1 links
8.192Mbps IBO interface to Dallas Semiconductor Framers/Transceivers
Differential delay compensation up to 7.75ms for the 4 T1/E1 links
Handshaking protocol between local and distant end for establishment of aggregation
Dedicated HDLC controller engine for protocol encapsulation
Compatible with polled or interrupt driven environments
Programmable FCS insertion and extraction
Programmable FCS type
Supports FCS error insertion
Programmable packet size limits (minimum 64 bytes and maximum 2016 bytes)
Supports bit stuffing/destuffing
Selectable packet scrambling/descrambling (X
Separate FCS errored packet and aborted packet counts
Programmable inter-frame fill for transmit HDLC
Programmable X.86 address/control fields for transmit and receive
Programmable 2-byte protocol (SAPI) field for transmit and receive
32-bit FCS
Transmit transparency processing—7E is replaced by 7D, 5E
Transmit transparency processing—7D replaced by 7D, 5D
Receive rate adaptation (7D, DD) is deleted.
Receive transparency processing—7D, 5E is replaced by 7E
Receive transparency processing—7D, 5D is replaced by 7D
Receive abort sequence the LAPS packet is dropped if 7D7E is detected
Self-synchronizing X
43
+ 1 payload scrambling.
11 of 335
43
+1)