DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 33

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
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FUNCTIONAL DESCRIPTION
The DS33R41 provides interconnection and mapping functionality between Ethernet Packet Systems and T1/E1/J1
WAN Time-Division Multiplexed (TDM) systems. The device is composed of a 10/100 Ethernet MAC, Packet
Arbiter, Committed Information Rate Controller (CIR), HDLC/X.86 (LAPS) Mapper, SDRAM interface, control ports,
four Bit Error Rate Testers (BERTs), and four integrated T1/E1/J1 Transceivers. The packet interface consists of a
MII/RMII Ethernet PHY interface. The Ethernet interface can be configured for 10Mbps or 100Mbps service. The
DS33R41 encapsulates Ethernet traffic with HDLC or X.86 (LAPS) encoding to be transmitted over up to four T1,
E1, or J1 lines. The T1/E1/J1 interfaces also receive encapsulated Ethernet packets and transmit the extracted
packets over the Ethernet ports. Access is provided between the Serial port and the integrated T1/E1/J1
Transceivers to the intermediate signal bus that is based on the Dallas Semiconductor Integrated Bus Operation
(IBO), running at 8.192Mbps.
The Ethernet Packet interface supports both MII and RMII mode, allowing the DS33R41 to connect to
commercially available Ethernet PHY and MAC devices. The Ethernet interface can be individually configured for
10Mbps or 100Mbps service, in DTE and DCE configurations. The DS33R41 MAC interface can be configured to
reject frames with bad FCS and short frames (less than 64 bytes).
Ethernet frames are queued and stored in external 32-bit SDRAM. The DS33R41 SDRAM controller enables
connection to a 128Mbit SDRAM without external glue logic, at clock frequencies up to 100MHz. The SDRAM is
used for both the Transmit and Receive Data Queues. The Receive Queue stores data to be sent from the Packet
interface to the WAN interface. The Transmit Queue stores data to be sent from the WAN interface to the Packet
interface. The external SDRAM can accommodate up to 8192 frames with a maximum frame size of 2016 bytes.
The sizing of the queues can be adjusted by software. The user can also program high and low watermarks for
each queue that can be used for automatic or manual flow control. The packet data stored in the SDRAM is
encapsulated in HDLC or X.86 (LAPS) to be transmitted over the WAN interfaces. The device also provides the
capability for bit and packet scrambling.
The WAN interface also receives encapsulated Ethernet packets and transmits the extracted packets over the
Ethernet port. The WAN physical interface supports up to 4 serial data streams on a 8.192Mbps IBO bus. The
WAN serial port can operate with a gapped clock, and can be connected to a framer or T/E-Carrier transceiver for
transmission to the WAN. The WAN interface can be seamlessly connected to the Dallas Semiconductor/Maxim
T1/E1/J1 Framers and Single-Chip Transceivers (SCTs).
The DS33R41 can be configured through an 8-bit microprocessor interface port. The DS33R41 also provides 2 on-
board clock dividers for the System Clock input and Reference Clock Input for the 802.3 interfaces, further
reducing the need for ancillary devices.
The four integrated T1/E1/J1 transceivers can be software configured for T1, E1, or J1 operation. Each transceiver
is composed of a line interface unit (LIU), framer, dual HDLC controllers, and a TDM backplane interface. The
transceivers are software compatible with the DS21455, DS21458, and the older DS21Q55.
The LIU is composed of a transmit interface, receive interface, and a jitter attenuator. The transmit interface is
responsible for generating the necessary waveshapes for driving the network and providing the correct source
impedance depending on the type of media used. T1 waveform generation includes DSX-1 line build-outs as well
as CSU line build-outs of -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes G.703 waveshapes for
both 75Ω coax and 120Ω twisted cables. The receive interface provides network termination and recovers clock
and data from the network. The receive sensitivity adjusts automatically to the incoming signal and can be
programmed for 0dB to 43dB or 0dB to 12dB for E1 applications and 0dB to 15dB or 0dB to 36dB for T1
applications. The jitter attenuator removes phase jitter from the transmitted or received signal. The crystal-less jitter
attenuator requires only a 2.048MHz MCLK for both E1 and T1 applications (with the option of using a 1.544MHz
MCLK in T1 applications) and can be placed in either transmit or receive data paths.
On the transmit side, clock/data, and frame-sync signals are provided to the framer by the backplane interface
section. The framer inserts the appropriate synchronization framing patterns and alarm information, calculates and
inserts the CRC codes, and provides the B8ZS/HDB3 (zero code suppression) and AMI line coding. The receive-
side framer decodes AMI, B8ZS, and HDB3 line coding, synchronizes to the data stream, reports alarm
information, counts framing/coding/CRC errors, and provides clock/data and frame-sync signals to the backplane
interface section.
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