DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 251

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 6: Transmit-Clock Edge Select (TCES). Selects which TDCLKI edge to sample TPOSI and TNEGI.
Bit 5: Receive-Clock Edge Select (RCES). Selects which RCLKOn edge to update RPOSO and RNEGO.
Bits 3 and 4: Monitor Mode (MM1 and MM0)
Bit 2: Receive Synchronization G.703 Clock Enable (RSCLKE)
Bit 1: Transmit Synchronization G.703 Clock Enable (TSCLKE)
Bit 0: Transmit Alternate Ones and Zeros (TAOZ). Transmit a …101010… pattern (customer disconnect
indication signal) at TTIP and TRING. The transmission of this data pattern is always timed off of TCLKT.
MM1
0
0
1
1
0 = sample TPOSI and TNEGI on falling edge of TDCLKI
1 = sample TPOSI and TNEGI on rising edge of TDCLKI
0 = update RPOSO and RNEGO on rising edge of RCLKOn
1 = update RPOSO and RNEGO on falling edge of RCLKOn
0 = disable 1.544MHz (T1)/2.048MHz (E1) synchronization receive mode
1 = enable 1.544MHz (T1)/2.048MHz (E1) synchronization receive mode
0 = disable 1.544MHz (T1)/2.048MHz (E1) transmit synchronization clock
1 = enable 1.544MHz (T1)/2.048MHz (E1) transmit synchronization clock
0 = disabled
1 = enabled
MM0
0
1
0
1
—
7
0
Internal Linear Gain Boost
Normal operation (no boost)
TR.LIC3
Line Interface Control 3
7Ah
TCES
6
0
(dB)
20
26
32
RCES
5
0
251 of 335
MM1
4
0
MM0
3
0
RSCLKE
2
0
TSCLKE
1
0
TAOZ
0
0