DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 35
DS33R41
Manufacturer Part Number
DS33R41
Description
Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33R41.pdf
(335 pages)
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DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
8.1.1 Read-Write/Data Strobe Modes
The processor interface can operate in either read-write strobe mode or data strobe mode. When MODEC = 00 the
read-write strobe mode is enabled and a negative pulse on RD performs a read cycle, and a negative pulse on WR
performs a write cycle. When MODEC = 01 the data strobe mode is enabled and a negative pulse on DS when RW
is high performs a read cycle, and a negative pulse on DS when RW is low performs a write cycle. The read-write
strobe mode is commonly called the “Intel” mode, and the data strobe mode is commonly called the “Motorola”
mode. See the timing diagrams in the AC Electrical Characteristics for more details.
8.1.2 Clear on Read
The latched status registers will clear on a read access. It is important to note that in a multi-task software
environment, the user should handle all status conditions of each register at the same time to avoid inadvertently
clearing status conditions. The latched status register bits are carefully designed so that an event occurrence
cannot collide with a user read access.
8.1.3 Interrupt and Pin Modes
The interrupt (INT) pin is configurable to drive high or float when not active. The INTM bit controls the pin
configuration, when it is set the INT pin will drive high when not active. After reset, the INT pin is in high impedance
mode until an interrupt source is active and enabled to drive the interrupt pin.
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