DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 6

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
LIST OF FIGURES
Figure 3-1. Quad T1E1 SCT to DS33R41 ...........................................................................................................................15
Figure 6-1. Detailed Block Diagram ....................................................................................................................................18
Figure 6-2. T1/E1/J1 Transceiver Block Diagram ...............................................................................................................19
Figure 6-3. Framer/LIU Interim Signals ...............................................................................................................................20
Figure 7-1. DS33R41 400-Ball BGA Pinout.........................................................................................................................32
Figure 9-1. Clocking for the DS33R41 ................................................................................................................................37
Figure 9-2. Device Interrupt Information Flow Diagram ......................................................................................................42
Figure 9-3. IMUX Interface to T1/E1 Transceivers..............................................................................................................44
Figure 9-4. Diagram of Data Transmission with IMUX Operation .......................................................................................44
Figure 9-5. Command Structure for IMUX Function............................................................................................................46
Figure 9-6. Flow Control Using Pause Control Frame ........................................................................................................52
Figure 9-7. IEEE 802.3 Ethernet Frame..............................................................................................................................54
Figure 9-8. Configured as DTE Connected to an Ethernet PHY in MII Mode .....................................................................56
Figure 9-9. DS33R41 Configured as a DCE in MII Mode....................................................................................................57
Figure 9-10. RMII Interface .................................................................................................................................................59
Figure 9-11. MII Management Frame..................................................................................................................................60
Figure 9-12. HDLC Encapsulation of MAC Frame ..............................................................................................................63
Figure 9-13. LAPS Encoding of MAC Frames Concept ......................................................................................................64
Figure 9-14. X.86 Encapsulation of the MAC field ..............................................................................................................65
Figure 10-1. Transceiver Clock Structure............................................................................................................................68
Figure 10-2. Normal Signal Flow Diagram ..........................................................................................................................74
Figure 10-3. Simplified Diagram of Receive Signaling Path................................................................................................80
Figure 10-4. Simplified Diagram of Transmit Signaling Path...............................................................................................82
Figure 10-5. CRC-4 Recalculate Method ............................................................................................................................88
Figure 10-6. Typical Monitor Application .............................................................................................................................99
Figure 10-7. CMI Coding ...................................................................................................................................................101
Figure 10-8. Basic Interface ..............................................................................................................................................102
Figure 10-9. E1 Transmit Pulse Template.........................................................................................................................103
Figure 10-10. T1 Transmit Pulse Template.......................................................................................................................103
Figure 10-11. Jitter Tolerance ...........................................................................................................................................104
Figure 10-12. Jitter Tolerance (E1 Mode) .........................................................................................................................104
Figure 10-13. Jitter Attenuation (T1 Mode) .......................................................................................................................105
Figure 10-14. Jitter Attenuation (E1 Mode) .......................................................................................................................105
Figure 10-15. Optional Crystal Connections .....................................................................................................................106
Figure 10-16. Simplified Diagram of BERT in Network Direction ......................................................................................108
Figure 10-17. Simplified Diagram of BERT in Backplane Direction...................................................................................108
Figure 11-1. IBO Interconnection Example .......................................................................................................................112
Figure 11-2. T1/J1 Transmit Flow Diagram.......................................................................................................................114
Figure 11-3. E1 Transmit Flow Diagram ...........................................................................................................................116
Figure 13-1. MII Transmit Functional Timing.....................................................................................................................294
Figure 13-2. MII Transmit Half Duplex with a Collision Functional Timing ........................................................................294
Figure 13-3. MII Receive Functional Timing......................................................................................................................295
Figure 13-4. RMII Transmit Interface Functional Timing ...................................................................................................295
Figure 13-5. RMII Receive Interface Functional Timing ....................................................................................................295
Figure 13-6. Receive Side D4 Timing ...............................................................................................................................296
Figure 13-7. Receive Side ESF Timing .............................................................................................................................296
Figure 13-8. Receive Side 1.544MHz Boundary Timing (With Elastic Store Enabled) .....................................................297
Figure 13-9. Receive Side 2.048MHz Boundary Timing (With Elastic Store Enabled) .....................................................297
Figure 13-10. Transmit Side D4 Timing ............................................................................................................................298
Figure 13-11. Transmit Side ESF Timing ..........................................................................................................................298
Figure 13-12. Transmit Side 1.544MHz Boundary Timing (With Elastic Store Enabled) ..................................................299
Figure 13-13. Transmit Side 2.048MHz Boundary Timing (With Elastic Store Enabled) ..................................................299
Figure 13-14. Receive Side Timing ...................................................................................................................................300
Figure 13-15. Receive Side Boundary Timing, RSYSCLK = 1.544MHz (With Elastic Store Enabled)..............................300
Figure 13-16. Receive Side Boundary Timing, RSYSCLK = 2.048MHz (With Elastic Store Enabled)..............................301
Figure 13-17. Receive IBO Channel Interleave Mode Timing ..........................................................................................301
Figure 13-18. G.802 Timing, E1 Mode Only......................................................................................................................302
Figure 13-19. Transmit Side Timing ..................................................................................................................................302
Figure 13-20. Transmit Side Boundary Timing (With Elastic Store Disabled) ...................................................................303
Figure 13-21. Transmit Side Boundary Timing, TSYSCLK = 1.544MHz (With Elastic Store Enabled) .............................303
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