DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 180

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
0014h:
Bit #
Name
Default
0015h:
Bit #
Name
Default
0016h:
Bit #
Name
Default
0017h:
Bit #
Name
Default
Bits 15 to 11: PHY Address (PHYA[4:0]). These 5 bits select one of the 32 available PHY address locations to
access through the PHY management (MDIO) bus.
Bits 10 to 6: MII Address (MIIA[4:0]). These 5 bits are the address location within the PHY that is being
accessed.
Bit 1: MII Write (MIIW). Write this bit to 1 in order to execute a write instruction over the MDIO interface. Write the
bit to zero to execute a read instruction.
Bit 0: MII Busy (MIIB). This bit is set to 1 by the device during execution of a MII management instruction through
the MDIO interface, and is set to zero when the device has completed the instruction. The user should read this bit
and ensure that it is equal to zero prior to beginning a MDIO instruction.
Reserved
Reserved
PHYA4
MIIA1
31
23
15
07
0
0
0
1
Reserved
Reserved
PHYA3
MIIA0
06
30
22
14
1
0
0
1
SU.MACMIIA
MAC MII Management (MDIO) Address Register
0014h (indirect)
Reserved
Reserved
Reserved
PHYA2
05
29
21
13
0
0
0
0
Reserved
Reserved
Reserved
PHYA1
180 of 335
28
20
12
04
0
0
1
0
Reserved
Reserved
Reserved
PHYA0
27
19
11
03
0
0
1
0
Reserved
Reserved
Reserved
MIIA4
26
18
10
02
0
0
0
0
Reserved
Reserved
MIIA3
MIIW
25
17
09
01
0
0
0
1
Reserved
Reserved
MIIA2
MIIB
00
24
16
08
0
0
0
0