DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 139

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: IMUX Transmit OOF Interrupt Enable 4 (TOOFIE4). Setting this bit to 1 enables an interrupt on TOOFLS4.
Bit 6: IMUX Transmit OOF Interrupt Enable 3 (TOOFIE3). Setting this bit to 1 enables an interrupt on TOOFLS3.
Bit 5: IMUX Transmit OOF Interrupt Enable 2 (TOOFIE2). Setting this bit to 1 enables an interrupt on TOOFLS2.
Bit 4: IMUX Transmit OOF Interrupt Enable 1 (TOOFIE1). Setting this bit to 1 enables an interrupt on TOOFLS1.
Bit 3: IMUX Receive OOF Interrupt Enable 4 (ROOFIE4). Setting this bit to 1 enables an interrupt on ROOFLS4.
Bit 2: IMUX Receive OOF Interrupt Enable 3 (ROOFIE3). Setting this bit to 1 enables an interrupt on ROOFLS3.
Bit 1: IMUX Receive OOF Interrupt Enable 2 (ROOFIE2). Setting this bit to 1 enables an interrupt on ROOFLS2.
Bit 0: IMUX Receive OOF Interrupt Enable 1 (ROOFIE1). Setting this bit to 1 enables an interrupt on ROOFLS1.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: IMUX Transmit OOF Latched Status 4 (TOOFLS4). This is a latched bit for Transmit OOF, this bit is set if
the distant end is out of frame.
Bit 6: IMUX Transmit OOF Latched Status 3 (TOOFLS3). This is a latched bit for Transmit OOF, this bit is set if
the distant end is out of frame.
Bit 5: IMUX Transmit Sync Latched Status 2 (TOOFLS2). This is a latched bit for Transmit OOF, this bit is set if
the distant end is out of frame.
Bit 4: IMUX Transmit Sync Latched Status 1 (TOOFLS1). This is a latched bit for Transmit OOF , this bit is set if
the distant end is out of frame.
Bit 3: IMUX Receive Sync Latched Status 4 (ROOFLS4). This is a latched bit for Receiver OOF, this bit is set if
the receiver end is out of frame.
Bit 2: IMUX Receive Sync Latched Status 3 (ROOFLS3). This is a latched bit for Receiver OOF, this bit is set if
the receiver end is out of frame.
Bit 1: IMUX Receive Sync Latched Status 2 (ROOFLS2). This is a latched bit for Receiver OOF, this bit is set if
the receiver end is out of frame.
Bit 0: IMUX Receive Sync Latched Status 1 (ROOFLS1). This is a latched bit for Receiver OOF, this bit is set if
the receiver end is out of frame.
Note that the user must clear the GL.IMXCN.SENDE bit to stop data transmission when an OOF condition is
detected. The user must re-initiate the handshaking procedure for re-establishment of communication.
TOOFLS4
TOOFIE4
7
0
7
0
TOOFIE3
OOFLS3
6
0
6
0
GL.IMXOOFIE
Inverse MUX OOF Interrupt Enable
1Eh
GL.IMXOOFLS
Inverse MUX Out Of Frame Latched Status
1Fh
TOOFLS2
TOOFIE2
5
0
5
0
TOOFLS1
TOOFIE1
139 of 335
0
4
0
4
ROOFIE4
ROOFL4
3
0
3
0
ROOFIE3
ROOFL3
2
0
2
0
ROOFLS2
ROOFIE2
1
0
1
0
ROOFLS1
ROOFIE1
0
0
0
0