DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 331

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

15.3 Instruction Register
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the
TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDIn and JTDOn.
While in the Shift-IR state, a rising edge on JTCLKn with JTMSn LOW will shift the data one stage towards the
serial output at JTDOn. A rising edge on JTCLKn in the Exit1-IR state or the Exit2-IR state with JTMSn HIGH will
move the controller to the Update-IR state. The falling edge of that same JTCLKn will latch the data in the
instruction shift register to the instruction parallel output. Instructions supported by the device and its respective
operational binary codes are shown in
Table 15-1. Instruction Codes for IEEE 1149.1 Architecture
15.3.1 SAMPLE:PRELOAD
This is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The
digital I/Os of the device can be sampled at the boundary scan register without interfering with the normal
operation of the device by using the Capture-DR state. SAMPLE:PRELOAD also allows the device to shift data into
the boundary scan register via JTDIn using the Shift-DR state.
15.3.2 BYPASS
When the BYPASS instruction is latched into the parallel instruction register, JTDIn connects to JTDOn through the
one-bit bypass test register. This allows data to pass from JTDIn to JTDOn not affecting the device’s normal
operation.
15.3.3 EXTEST
This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the instruction
register, the following actions occur. Once enabled via the Update-IR state, the parallel outputs of all digital output
pins are driven. The boundary scan register is connected between JTDIn and JTDOn. The Capture-DR will sample
all digital inputs into the boundary scan register.
15.3.4 CLAMP
All digital outputs of the device will output data from the boundary scan parallel output while connecting the bypass
register between JTDIn and JTDOn. The outputs will not change during the CLAMP instruction.
15.3.5 HIGHZ
All digital outputs of the device are placed in a high-impedance state. The BYPASS register is connected between
JTDIn and JTDOn.
15.3.6 IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the identification test register is
selected. The device identification code is loaded into the identification register on the rising edge of JTCLKn
following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially via
JTDOn. During Test-Logic-Reset, the identification code is forced into the instruction register’s parallel output. The
ID code will always have a ‘1’ in the LSB position. The next 11 bits identify the manufacturer’s JEDEC number and
number of continuation bytes followed by 16 bits for the device and 4 bits for the version.
SAMPLE:PRELOAD
INSTRUCTION
BYPASS
EXTEST
IDCODE
CLAMP
HIGHZ
SELECTED REGISTER
Device Identification
Table
Boundary Scan
Boundary Scan
15-1.
Bypass
Bypass
Bypass
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INSTRUCTION CODES
010
111
000
011
100
001