DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 153

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

12.5.5 Receive Serial Interface
Serial Receive Registers are used to control the HDLC Receiver associated with each Serial Interface. Note that
throughout this document HDLC Processor is also referred to as “Packet Processor.” The receive packet
processor block has 17 registers.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 5: Receive FCS Processing Disable (RFPD). When equal to 0, FCS processing is performed and FCS is
appended to packets. When set to 1, FCS processing is disabled (the packets do not have an FCS appended). In
X.86 mode, FCS processing is always enabled.
Bit 4: Receive FCS-16 Enable (RF16). When 0, the error checking circuit uses a 32-bit FCS. When 1, the error
checking circuit uses a 16-bit FCS. This bit is ignored when FCS processing is disabled. In X.86 mode, the FCS is
always 32 bits.
Bit 3: Receive FCS Extraction Disable (RFED). When 0, the FCS bytes are discarded. When 1, the FCS bytes
are passed on. This bit is ignored when FCS processing is disabled. In X.86 mode, FCS bytes are discarded.
Bit 2: Receive Descrambling Disable (RDD). When equal to 0, X
1, descrambling is disabled.
Bit 1: Receive Bit Reordering Enable (RBRE). When equal to 0, reordering is disabled and the first bit received
is expected to be the MSB DT [7] of the byte. When set to 1, bit reordering is enabled and the first bit received is
expected to be the LSB DT [0] of the byte. Note that function is controlled by the BREO in Hardware Mode.
Bit 0: Receive Clear Channel Enable (RCCE). When equal to 0, packet processing is enabled. When set to 1, the
device is in clear channel mode and all packet-processing functions except descrambling and bit reordering are
disabled.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Receive Maximum Packet Size (RMX[7:0]). Eight bits of a 16-bit value. Register description below.
RMX7
—
7
0
7
1
RMX6
—
6
0
6
1
LI.RPPCL
Receive Packet Processor Control Low Register
101h
LI.RMPSCL
Receive Maximum Packet Size Control Low Register
102h
RMX5
RFPD
5
0
5
1
153 of 335
RMX4
RF16
0
0
4
4
RMX3
RFED
43
3
0
3
0
+ 1 descrambling is performed. When set to
RMX2
RDD
2
0
2
0
RBRE
RMX1
1
0
1
0
RCCE
RMX0
0
0
0
0