DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 328

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
15.1 JTAG TAP Controller State Machine Description
This section covers the details on the operation of the Test Access Port (TAP) Controller State Machine. The TAP
controller is a finite state machine that responds to the logic level at JTMSn on the rising edge of JTCLKn.
15.2 TAP Controller State Machine
The TAP controller is a finite state machine that responds to the logic level at JTMSn on the rising edge of
JTCLKn. See
Figure 15-2
for a diagram of the state machine operation.
15.2.1 Test-Logic-Reset
Upon power up, the TAP Controller is in the Test-Logic-Reset state. The Instruction register will contain the
IDCODE instruction. All system logic of the device will operate normally.
15.2.2 Run-Test-Idle
The Run-Test-Idle is used between scan operations or during specific tests. The Instruction register and test
registers will remain idle.
15.2.3 Select-DR-Scan
All test registers retain their previous state. With JTMSn LOW, a rising edge of JTCLKn moves the controller into
the Capture-DR state and will initiate a scan sequence. JTMSn HIGH during a rising edge on JTCLKn moves the
controller to the Select-IR-Scan state.
15.2.4 Capture-DR
Data may be parallel-loaded into the test data registers selected by the current instruction. If the instruction does
not call for a parallel load or the selected register does not allow parallel loads, the test register will remain at its
current value. On the rising edge of JTCLKn, the controller will go to the Shift-DR state if JTMSn is LOW or it will
go to the Exit1-DR state if JTMSn is HIGH.
15.2.5 Shift-DR
The test data register selected by the current instruction is connected between JTDIn and JTDOn and will shift
data one stage towards its serial output on each rising edge of JTCLKn. If a test register selected by the current
instruction is not placed in the serial path, it will maintain its previous state.
15.2.6 Exit1-DR
While in this state, a rising edge on JTCLKn will put the controller in the Update-DR state, which terminates the
scanning process, if JTMSn is HIGH. A rising edge on JTCLKn with JTMSn LOW will put the controller in the
Pause-DR state.
15.2.7 Pause-DR
Shifting of the test registers is halted while in this state. All test registers selected by the current instruction will
retain their previous state. The controller will remain in this state while JTMSn is LOW. A rising edge on JTCLKn
with JTMSn HIGH will put the controller in the Exit2-DR state.
15.2.8 Exit2-DR
A rising edge on JTCLKn with JTMSn HIGH while in this state will put the controller in the Update-DR state and
terminate the scanning process. A rising edge on JTCLKn with JTMSn LOW will enter the Shift-DR state.
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