SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 102

• Manufacturer Part Number: SAA7115HLBE
• Description: Video ICs ADV DGTL VIDEO DECODR
• Manufacturer: NXP Semiconductors

Specifications of SAA7115HLBE

• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-407
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Resolution: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7115HL/V1,557 SAF7115HLBE

PNX1300/01/02/11 Data Book
mat by vertical subsampling with a (1 1) / 2 or more so-
phisticated filter. Vertical filtering can be performed in
software using the DSPCPU’s efficient multimedia oper-
ations or by hardware in the on-chip ICP.
The filtering process exercises special care at the left
and right edges of the active area of the CCIR656 data
stream, as defined by the SAV, EAV code positions. See
Figure
el or to the right of the last pixel, filtering can result in ar-
tifacts. To minimize artifacts, the image is extended by
mirroring pixels around the left-most and right-most pixel.
Note that the image is mirrored around pixel ‘a’, the first
pixel after the SAV code and around pixel ‘zz’, the last
pixel before the EAV
(chroma, luma) pair defined by the first three camera
bytes of the UYVYUYVY... stream after SAV.
Refer to
mapped I/O (MMIO) registers that are used to control
and observe the operation of VI in fullres capture mode.
To ensure compatibility with future devices, any unde-
fined MMIO bits should be ignored when read and written
as’0’s.
Upon hardware or software reset
ware and Software
and VI_CLOCK registers are set to all zeros.
At any point in time, the VI_STATUS register fields (see
Figure
• CUR_X: The pixel index (0 to M–1) of the most
• CUR_Y: The line index (0 to N–1) within the current
• FIELD2: Indicates whether the field currently being
Table 6-3
and the number of active pixels per line, lines per field,
and fields per second. Note that any source is accept-
able to VI, as long as the maximum VI_CLK rate is not
exceeded.
Figure 6-9
captured image. The incoming field consists of N hori-
6-6
1.
2.
recently received camera pixel. CUR_X gets set to
zero for the first pixel following receipt of a SAV
code
received thereafter.
field of the camera line that is currently being
received. CUR_Y gets set to zero upon receipt of a
negative edge of V, i.e., upon the first SAV code con-
taining V=0 after one or more SAV codes containing
V=1. This is equivalent to the first line after the end of
vertical retrace. CUR_Y gets incremented upon
every successive SAV code.
received is a field1 or 2. This flag gets updated based
on the F field of every received SAV code. Note that
field1 is the ‘top’ field, i.e. the field containing the top-
most visible line. Field1 contains lines 1,3,5 etc.
Field2 contains lines 2,4,6,8 etc.
EAV codes with multiple bit errors are accepted and en-
able the mirroring function.
Note that VI uses the SAV protection bits to implement
single error correction and double error detection. An
SAV code with double error is ignored.
6-7. Since no pixels exist to the left of the first pix-
6-11) indicate the current camera status:
2
, and incremented on every valid Y sample
Figure 6-11
illustrates common digital camera standards
shows the details of an incoming field and the
Reset”), the VI_CTL, VI_STATUS,
1
PRELIMINARY SPECIFICATION
code. Pixel ‘a’ in
for an overview of the memory
(Section 6.1.4, “Hard-
Figure 6-7
is the
Table 6-3. Common video source parameters.
zontal lines, each line having M pixels labeled 0 through
M–1. Lines are numbered from 0 through N–1. The cap-
tured image is a subset of the incoming image. It is de-
fined by the capture parameters (START_X, START_Y,
WIDTH, HEIGHT) held in the VI_CAP_START and
VI_CAP_SIZE MMIO registers (see
• START_X: defines the starting pixel number (X-coor-
• START_Y: defines the starting line number (Y-coor-
• WIDTH: Defines the width of the captured image in
• HEIGHT: Defines the height of the captured image in
Image capture starts after the following conditions are
met:
• VI_CTL.CAPTURE ENABLE is asserted.
• VI_STATUS.CAPTURE COMPLETE is de-asserted,
• CUR_Y = START_Y occurs.
Once image capture is started, HEIGHT ‘lines’ are cap-
tured. Each line capture starts if:
• The previous line capture, if any, is completed.
• CUR_X = START_X
Once line capture starts, it continues for 2*WIDTH pixel
clocks
the presence of one or more EAV codes.
Note that capture continues regardless of any horizontal
or vertical retrace and associated CUR_Y or CUR_X re-
set. This provides special applications with the ability to
capture information embedded inside the horizontal or
vertical blanking interval. If it is desirable to capture pix-
els in the horizontal blanking interval, a minimum time
separation of 1 µs is required between the last pixel cap-
tured on line y and the first pixel captured on line y+1. An
exception to this rule is allowed if and only if the storage
parameters below are chosen such that the last and first
CCIR601
50 Hz/625 lines
CCIR601
60 Hz/525 lines
square pixel
50 Hz/625 lines
square pixel
60 Hz/525 lines
Video Source
3.
dinate of the starting pixel). START_X must be even,
and greater than or equal to ‘0’.
dinate of the starting pixel). START_Y must be
greater than or equal to ‘0’.
pixels. WIDTH must be even.
lines.
indicating that any previously captured image has
been acknowledged.
Four clocks for each C
luminance pixels
3
in which VI_DVALID is asserted, irrespective of
(# active pixels)
720
720
768
640
M
b
,Y,C
Philips Semiconductors
r
,Y group representing two
(# active lines)
Figure
288
240
288
240
N
6-11).
Field
Rate
(Hz)
50
60
50
60