SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 119

Video ICs ADV DGTL VIDEO DECODR

SAA7115HLBE

Manufacturer Part Number
SAA7115HLBE
Description
Video ICs ADV DGTL VIDEO DECODR
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SAA7115HLBE

Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 70 C
Package / Case
SOT-407
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Number Of Channels
2
Resolution
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
SAA7115HL/V1,557 SAF7115HLBE
Philips Semiconductors
Figure 7-18. Message-passing START and END signals.
the first byte of the first line just after the VO_IO2 active
signal.
7.11
In data-streaming and message-passing modes, the
EVO supplies a stream of 8-bit data. No data selection or
data interpretation is done, and data is transferred at the
rate of one byte per VO_CLK. Data is clocked out on the
positive edge of VO_CLK.
When
EVO_ENABLE = 1 and SYNC_STREAMING = 1, the
VO_IO2 signal indicates a data-valid condition. This sig-
nal is asserted when the EVO starts outputting valid data
(that is, data-streaming mode is enabled and video out is
running), and is de-asserted when data-streaming mode
is disabled. As shown in
nal on VO_IO2 is asserted just before the first valid byte
is present on VO_DATA[7:0], and is de-asserted just af-
ter the last valid byte was sent, or if an HBE error is sig-
naled. All transitions of VO_IO2 occur on the rising edge
of VO_CLK. The VO_IO1 signal generates a pulse one
VO_CLK cycle before the first valid data is sent. The
Figure 7-17. Data-streaming valid data signals.
Figure 7-16. Genlock mode.
VO_DATA[7:0]
Image Data
VO_DATA[7:0]
VO_CLK
DATA TRANSFER TIMING
VO_IO1
VO_IO2
data-streaming
VO_CLK
VO_IO2
VO_IO1
VO_IO2
Line 525/625
message
Delay SLAVE_DLY in VO_CLK cycles
Start of
XX
Figure
mode
XX
7-17, the data-valid sig-
D0
EAV
XX
Line 1
is
D1
enabled
D0
D2
D1
Line 2
and
One Frame
D3
DATA_VALID
D2
transitions of VO_IO1 occur on the rising edge of
VO_CLK and last for one VO_CLK cycle.
In message-passing mode, the EVO issues signals on
VO_IO1 and VO_IO2 to indicate the start and end of
messages.
When message passing is started by setting VO_CTL.
VO_ENABLE, the EVO sends a Start condition on
VO_IO1. When the EVO has transferred the contents of
the buffer, it sends an End condition on VO_IO2, sets
BFR1_EMPTY, and interrupts the DSPCPU. The EVO
stops, and no further operation takes place until the
DSPCPU sets VO_ENABLE again to start another mes-
sage, or until the DSCPU initiates other EVO operation.
The timing for these signals is shown in
7.12
7.12.1
The EVO accepts memory-resident video image data in
three formats: YUV 4:2:2 co-sited, YUV 4:2:2 inter-
spersed, and YUV 4:2:0. These formats are shown in
Figure 7-19
PRELIMINARY SPECIFICATION
D4
Line counter loaded by FRAME_PRESET
Line FRAME_PRESET
EAV
D3
IMAGE DATA MEMORY FORMATS
D5
Video Image Formats
through
D4
D6
Figure
D5
Line 525/625
message
End of
D7
7-21.
Dk
Enhanced Video Out
XX
EAV
Line 1
XX
Figure
XX
XX
7-18.
7-9

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