SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 148

• Manufacturer Part Number: SAA7115HLBE
• Description: Video ICs ADV DGTL VIDEO DECODR
• Manufacturer: NXP Semiconductors

Specifications of SAA7115HLBE

• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-407
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Resolution: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7115HL/V1,557 SAF7115HLBE

PNX1300/01/02/11 Data Book
9.4.2
TM-1000 clock compatibility mode is provided so that
TM-1000 audio software runs without changes. It should
NOT be used for new software development, due to a 3x
higher jitter. TM-1000 mode is automatically entered
whenever FREQUENCY[31] = 0. In TM-1000 mode,
AO_OSCLK frequency is set as follows:
9.5
The output of the DDS is always sent to the AO_OSCLK
output pin. This output is typically used as the 256f
384f
ers, such as the Philips SAA7322, or codecs such as the
AD1847, CS4218 or UD1340.
AO_WS and AO_SCK are sent to each external D/A con-
verter in the master mode.
AO_WS, the word strobe, determines the sample rate:
each active channel receives one sample for each
AO_WS period.
AO_SCK is the data bit clock. The number of AO_SCK
clocks in an AO_WS period is the number of data bits in
a serial frame required by the attached D/A converter.
AO_WS is a divider of the bit clock and is set using WS-
DIV to control the serial frame length. The number of bits
per frame is equal to WSDIV+1. There are some mini-
mum length requirements for a serial frame, refer to
Section
AO_SCK and AO_WS can be configured as input or out-
put, as determined by the SER_MASTER control field. If
set as output, AO_SCK can be set to a divider of the DDS
output frequency.
Whether set as input or output, the AO_SCK pin signal is
always used as the bit clock for parallel-serial conver-
sion. The AO_WS pin always acts as the trigger to start
the generation of a serial frame. AO_WS can similarly be
programmed using WSDIV to control the serial frame
length. The number of bits per frame is equal to WS-
DIV+1.
The preferred use of the clock system options is to use
AO_OSCLK as D/A master clock, and let the D/A con-
9-4
Figure 9-2. Definition of serial frame bit positions (POLARITY = 1, CLOCKEDGE = 0)
AO_WS
AO_SDx
AO_SCK
frame
s
f
system clock source for oversampling D/A convert-
AOSCK
n-1
FREQUENCY
CLOCK SYSTEM OPERATION
9.6.1.
30
TM-1000 Compatibility Mode
31
=
0
--------------------------------- -
SCKDIV
f
1
AOOSCLK
2
3
PRELIMINARY SPECIFICATION
+
=
4
1
5
f
----------------------------- -
3 f
OSCLK
⋅
6
DSPCPU
7
SCKDIV
8
⋅
2
9
32
10
∈
11
[ ,
12
0 255
13
]
14
15
s
or
16
frame
17
18
Table 9-4. AO MMIO Clock & Interface Control
verter be a timing slave of the serial interface
(SER_MASTER=1). This is important in view of compat-
ibility with future Trimedia devices, which may only sup-
port the AO unit as serial interface master.
Some D/A converters however, like the AD1847, provide
better SNR properties if they are configured as serial
master, with the AO unit as slave (SER_MASTER=0). As
illustrated by
converter that constructs the serial frame is oblivious to
which component is timing master.
9.6
The AO unit can generate data in a wide variety of serial
data framing conventions.
tion of a serial frame. If POLARITY=1, a frame starts with
a positive edge of the AO_WS signal. If POLARITY=0, a
serial frame starts with a negative edge on AO_WS. If
CLOCK_EDGE=0, the parallel to serial converter sam-
ples AO_WS on a positive clock edge transition, and out-
puts the first bit (bit 0) of a serial frame on the next falling
edge of AO_SCK.
If CLOCK_EDGE=1, the parallel to serial converter sam-
ples AO_WS on the negative edge of AO_SCK, while au-
dio data is output on the positive edge, i.e. the AO_SCK
polarity would be reversed with respect to
n
SER_MASTER
FREQUENCY
SCKDIV
WSDIV
19
Field Name
20
21
SERIAL DATA FRAMING
22
23
24
Figure
25
0 ⇒ (RESET default), the D/A subsystem
1 ⇒ PNX1300 is the timing master over
The SER_MASTER bit should only be
changed while the AO unit is disabled, i.e.
TRANS_ENABLE = 0.
Sets the clock frequency emitted by the
AO_OSCLK output. RESET default 0.
Sets the divider used to derive AO_SCK
from AO_OSCLK. Set to 0..255, for divi-
sion by 1..256. RESET default 0.
Sets the divider used to derive AO_WS
from AO_SCK. Set to 0..511 for a serial
frame length of 1..512. RESET default 0.
26
9-1, the internal parallel to serial
27
is the timing master over the AO
serial interface. AO_SCK and
AO_WS act as inputs.
the serial interface. AO_SCK and
AO_WS act as outputs. This mode is
required for 4,6 or 8 channel opera-
tion.
28
29
Philips Semiconductors
Figure 9-2
30
Description
31
0
1
illustrates the no-
2
frame
Figure
3
n+1
4
5
9-2.
6
7