SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 140

• Manufacturer Part Number: SAA7115HLBE
• Description: Video ICs ADV DGTL VIDEO DECODR
• Manufacturer: NXP Semiconductors

Specifications of SAA7115HLBE

• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-407
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Resolution: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7115HL/V1,557 SAF7115HLBE

PNX1300/01/02/11 Data Book
Table 8-5. AI MMIO serial framing control fields
In MSB-first mode, the serial-to-parallel converter as-
signs the value of the bit at LEFTPOS to LEFT[15]. Sub-
sequent bits are assigned, in order, to decreasing bit po-
sitions in the LEFT data word, up to and including
LEFT[SSPOS]. Bits LEFT[SSPOS–1:0] are cleared.
Hence, in MSB-first mode, an arbitrary number of bits are
captured. They are left-adjusted in the 16-bit parallel out-
put of the converter.
In LSB-first mode, the serial to parallel converter assigns
the value of the bit at LEFTPOS to LEFT[SSPOS]. Sub-
sequent bits are assigned, in order, to increasing bit po-
sitions in the LEFT data word, up to and including
LEFT[15]. Bits LEFT[SSPOS–1:0] are cleared. Hence, in
LSB-first mode, an arbitrary number of bits are captured.
They are returned left-adjusted in the 16-bit parallel out-
put of the converter.
Refer to
how the AI unit MMIO registers are set to collect 16-bit
samples using the Philips SAA7366 I
verter. This setup assumes the SAA7366 acts as the se-
rial master.
For example, if it were desirable to use only the 12 MSBs
of the A/D converter in
Table 8-6
LEFT[15:4] being set with data bits 0..11, and LEFT[3:0]
8-4
AI_SCK
Figure 8-3. Serial frame of the SAA7366 18 bit I
CLOCK_EDGE • if ‘0’(RESET default) the AI_SD and AI_WS
Figure 8-4. AI memory DMA formats.
AI_WS
AI_SD
Field Name
8-bit
mono
8-bit
stereo
16-bit
mono
16-bit
stereo
Figure 8-3
with SSPOS set to ‘4’. This results in
0
• if 1, AI_SD and AI_WS are sampled on neg-
pins are sampled on positive edges of the
AI_SCK pin. If SER_MASTER =1, AI_WS is
asserted on negative edges of AI_SCK.
ative edges of AI_SCK. As output, AI_WS
is asserted on positive edges of AI_SCK.
left
left
1
adr
adr
and
n
n
2
left
PRELIMINARY SPECIFICATION
3
n
Table 8-6
Figure
(18)
left
left
adr
adr
n
n
adr+1
left
adr+1
Description
right
8-3, use the settings of
n+1
n
to see an example of
2
S 18-bit A/D con-
18
19
adr+2
left
adr+2
left
n+2
n+1
31
left
adr+2
adr+2
right
2
32
S A/D converter (format 2 SWS).
n+1
n
33
right
adr+3
left
adr+3
34
right
n+3
n+1
n
(18)
being set to ’0’. RIGHT[15:4] is set with data bits 32..43
and RIGHT[3:0] is set to ’0’.
Table 8-6. Example setup for SAA7366
8.6
The AI unit autonomously writes samples to memory in
mono and stereo 8- and 16-bits per sample formats, as
shown in
stored at increasing memory address locations. The set-
SER_MASTER
FREQUENCY
SCKDIV
WSDIV
POLARITY
FRAMEMODE
VALIDPOS
LEFTPOS
RIGHTPOS
DATAMODE
SSPOS
CLOCK_EDGE
Field
adr+4
left
adr+4
left
MEMORY DATA FORMATS
n+4
n+2
Figure
50
left
left
adr+4
adr+4
51
n+2
n+1
161628209 256f
8-4. Successive samples are always
52
Value
n/a
right
63
00
32
adr+5
left
adr+5
0
3
0
0
0
0
0
n+5
n+2
62
Philips Semiconductors
SAA7366 is serial master
AI_SCK set to AI_OSCLK/4
(not needed since
SER_MASTER=0)
Serial frame length of 64 bits
(not needed since
SER_MASTER=0)
Frame starts with neg. AI_WS
Take a sample each ser.
frame
Bit position 0 is MSB of left
channel and will go to
LEFT[15]
Bit position 32 is MSB of right
channel and will go to
RIGHT[15]
MSB first
Stop with LEFT/RIGHT[0]
Sample WS and SD on posi-
tive SCK edges for I
Don’t care
63
0
s
44.1 kHz
adr+6
left
adr+6
left
1
n+6
n+3
Explanation
left
right
n+1
left
adr+6
adr+6
(18)
n+3
n+1
right
2
adr+7
left
adr+7
S
n+7
n+3