SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 178

• Manufacturer Part Number: SAA7115HLBE
• Description: Video ICs ADV DGTL VIDEO DECODR
• Manufacturer: NXP Semiconductors

Specifications of SAA7115HLBE

• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-407
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Resolution: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7115HL/V1,557 SAF7115HLBE

PNX1300/01/02/11 Data Book
PCI I/O read or write should not be performed during an
ongoing PCI configuration read or write.
The steps involved in a DSPCPU PCI I/O access are:
1. Wait until BIU_STATUS io_cycle.Busy and
2. Write IO address to IO_ADR, and (in case of a write
3. Write to IO_CTL to start the read or write.This action
4. Wait (polling or interrupt based) until io_cycle.Done is
5. Retrieve the requested data in IO_DATA (in case of a
6. Clear io_cycle.Done by writing a ‘1’ to it.
Following are descriptions of the fields of IO_CTL and a
discussion of how a DSPCPU write to IO_CTL triggers I/
O cycles.
BE (Byte enables). The BE field (the four least-signifi-
cant bits of IO_CTL) determines the state of PCI’s 4-line
c/be# bus during the data phase of an I/O cycle. Since
the c/be# bus signals are active low, a ‘0’ in a BE field bit
means ‘byte participates;’ a ‘1’ in a BE field bit means
‘byte does not participate.’
spondence between BE bits and bytes on the PCI bus
assuming little-endian byte order.
RW (Read/Write). The RW field (bit 4 of IO_CTL) deter-
mines whether the I/O cycle will be a read or a write.
Table 11-16
1 ⇒ read).
A write by the DSPCPU to the IO_CTL register starts an
I/O cycle on the PCI bus. The IO_DATA (for a write) and
IO_ADR registers must be set up before writing to
IO_CTL.
During an I/O read, the PCI interface drives the PCI bus
with the address from IO_ADR and the BE field from
IO_CTL. The returned data is buffered in IO_DATA.
When the data is returned, the PCI interface will gener-
ate a DSPCPU interrupt if the appropriate IntE bit is set
in BIU_CTL. Alternatively, DSPCPU software can poll
the appropriate ‘done’ status bit in BIU_STATUS. Finally,
DSPCPU software reads the IO_DATA register in MMIO
space to access the data returned from the I/O cycle.
A write operation proceeds as for a read, except that PCI
data is driven from IO_DATA during the transaction and
no data is returned in IO_DATA.
11.6.14 SRC_ADR Register
The 32-bit SRC_ADR register is used to set the source
address for a block transfer DMA operation. The address
in SRC_ADR must be word (4-byte) aligned, i.e. the 2
LSBs have to be ‘0’. The content of this register during or
after DMA is not defined, hence it cannot be used to track
progress or verify completion of a DMA transaction.
11-14
config_cycle.Busy are both de-asserted
operation) write data to IO_DATA.
sets io_cycle.Busy.
asserted by the hardware.
read)
shows the interpretation of RW (0 ⇒ write,
PRELIMINARY SPECIFICATION
Table 11-15
shows the corre-
11.6.15 DEST_ADR Register
The 32-bit DEST_ADR register is used to set the desti-
nation address for a block transfer DMA operation. The
address is DEST_ADR must be word (4 byte) aligned,
i.e. the 2 LSBs must be ‘0’. The content of this register
during or after DMA is not defined, hence it cannot be
used to track progress or verify completion of a DMA
transaction.
11.6.16 DMA_CTL Register
A write by the DSPCPU to the DMA_CTL register starts
a DMA block transfer on the PCI bus. The SRC_ADR
and DEST_ADR registers must be set up before writing
to DMA_CTL.
The steps involved in a DMA transfer are:
1. Wait until BIU_STATUS dma_cycle.Busy is de-as-
2. Write to SRC_ADR and DEST_ADR as described
3. Write to DMA_CTL to start the DMA transaction.This
4. Wait (polling or interrupt based) until dma_cycle.Done
5. Clear dma_cycle.Done by writing a ‘1’ to it
The fields of DMA_CTL are described below.
TL (Transfer length). The TL field (bits 0..25 of
DMA_CTL) specifies the number of data bytes to be
transferred during the DMA operation. It must be a multi-
ple of 4 bytes. The maximum length of a DMA operation
is limited to 64 MB, the maximum amount of SDRAM
supported by PNX1300. The content of this field during
or after a DMA transaction is not defined.
D (DMA direction). The D field (bit 26 of DMA_CTL) de-
termines the direction of data movement during the block
transfer.
field.
Table 11-17. D interpretation
T (DMA Transaction type). The T field (bit 27 of
DMA_CTL) determines the transaction type of a write, as
described below.
Table 11-18. T interpretation
serted
above
action sets dma_cycle.Busy
is asserted by the hardware
D
0
1
T
0
1
SDRAM → PCI memory space (DMA write)
PCI memory space → SDRAM (DMA read)
memory write
memory write-and-invalidate
Table 11-17
DMA Write transaction type
Data Movement Direction
(shows the interpretation of the D
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