SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 226
SAA7115HLBE
Manufacturer Part Number
SAA7115HLBE
Description
Video ICs ADV DGTL VIDEO DECODR
Manufacturer
NXP Semiconductors
Datasheet
1.SAA7115HLBE.pdf
(548 pages)
Specifications of SAA7115HLBE
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 70 C
Package / Case
SOT-407
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Number Of Channels
2
Resolution
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
SAA7115HL/V1,557 SAF7115HLBE
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up scaled by 2 relative to the Y component for YUV 4:4:4
output, although they could be up scaled as part of gen-
eral up scaling of the image.
The YUV 4:2:2 output mode also provides higher pro-
cessing bandwidth relative to YUV 4:4:4 up scaling. Half
as many U and V pixels are processed.The output pixel
rate is one pixel per 20 nanoseconds for the YUV 4:2:2
output mode versus one pixel per 30 for conversion to
YUV 4:4:4. This can be used to provide some processing
performance improvement for very large images at the
expense of some chroma quality.
14.5.9.2
The ICP outputs pixels to the PCI interface at a peak rate
of 33 Mpix/sec in RGB mode and 50 Mpix/second in the
14-16
Figure 14-16. ICP horizontal scaling for RGB output data flow block diagram
U LSB Counter
Y LSB Counter
V LSB Counter
B, BX Counter
Block FIFO
Block FIFO
Block FIFO
Buffers 0,1
Buffers 2,3
Buffers 4,5
Buffers 6,7
Y Counter
U Counter
V Counter
OL Counter
Bit Mask
Buffer 8
Overlay
FIFO
PCI output block timing
PRELIMINARY SPECIFICATION
Filter Source Select
Pixel
Clock
Reg
Reg
Reg
Reg
Reg
Reg
Reg
Reg
Reg
Reg
Reg
Reg
Sequence
Counter
YUV
Y Mirror Cntr
U Mirror Cntr
V Mirror Cntr
YUV mode using YUV sequencing. For one word per pix-
el output codes, such as RGB-24, this is a peak rate of
33 Mwords/sec or 132 Mpix/sec in the RGB sequencing
mode. This is the same speed as the 132 MB/sec peak
rate of the PCI interface. (At 50 Mpix/sec, the result
would be 200 MB/sec.) The BIU control for the PCI inter-
face has a FIFO for buffering data from the ICP, but this
buffer is only 16 words deep. Therefore, the ICP will oc-
casionally have to wait for the PCI to accept more data.
In the PCI output mode, this stalls the ICP clock.
14.6
The ICP uses a combination of hardware and a Micro-
program Control Unit (MCU) to implement its scaling, fil-
tering and conversion functions. The microprogram is a
Y, U, V Data FIFO Clocks
RGB to PCI case
RGB to SDRAM case
OPERATION AND PROGRAMMING
5 Stage Multiplier-
Accumulator
5-tap Filter
Y, U, V LSBs
Philips Semiconductors
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