SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 291

• Manufacturer Part Number: SAA7115HLBE
• Description: Video ICs ADV DGTL VIDEO DECODR
• Manufacturer: NXP Semiconductors

Specifications of SAA7115HLBE

• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-407
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Resolution: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7115HL/V1,557 SAF7115HLBE

Philips Semiconductors
signal so that only one EEPROM chip enable signal is
active at global chip enable time.
22.5
The PCI-XIO Bus Controller has one programmer visible
MMIO register: XIO_CTL. Its format is shown in
Table
any undefined MMIO bits should be ignored when read,
and written as ‘0’s.
Table 22-2. XIO_CTL Register Fields: MMIO Address
0x10 3060
22.5.1
PCI_CLK, the clock for the PCI and PCI-XIO bus can be
supplied externally or internally. This is determined at
Figure 22-9. Multiple 8-bit Flash EEPROM Interface
Address
Wait States
Enable
Clock Fre-
quency
PCI_INTB#
PCI_AD[19-17]
Field
22-2. To ensure compatibility with future devices,
XIO_CTL MMIO REGISTER
PCI_CLK Bus Clock Frequency
+3
31:26
25:11
Bits
10:8
6:5
4:0
7
XIO address space
unused
Wait states
Enable XIO Bus opera-
tion
unused
Clock divider
74FCT138
E2
E1
E0
A[2-0] O0
PCI_C/BE1#: IOWR#
PCI_C/BE0#: IORD#
Function
PCI_AD[16:0]
O1
O2
O3
O4
O5
O6
O7
128-256K
256-384K
384-512K
512-640K
640-768K
768-896K
896-1024K
0-128K
undefined
0
0
0 = disabled
0x1f
Reset Value
Output Enable
Chip Select
Output Enable
Chip Select
Address
Write Enable
Address
Write Enable
boot time, by the ‘enable internal PCI_CLK generator’ bit,
bit 6 of byte 9 in the boot EEPROM. Refer to
on page
with TM-1000 and normal PCI operation, i.e. PCI_CLK is
an input pin that takes the PCI clock from the external
world. If this bit = ‘1’, an on-chip clock divider in the XIO
logic becomes the source of PCI_CLK, and the PCI_CLK
pin is configured as an output. In the latter case, the
PCI_CLK frequency can be programmed to a divider of
the PNX1300 highway clock by setting the XIO_CTL reg-
ister ‘Clock Frequency’ divider value.
Table 22-3. PCI_CLK frequencies for 133.0 MHz
PNX1300 highway clock
PRELIMINARY SPECIFICATION
Frequency
128Kx8 EEPROM
128Kx8 EEPROM
(use odd
values)
Clock
30
31
...
0
1
2
3
13-2. If this bit = ‘0’, PCI_CLK acts compatible
PNX1300
Clocks
illegal
31
32
...
2
3
4
Data
Data
PCI-XIO External I/O Bus
PCI-XIO Clock
Period, ns
illegal
22.5
233
241
15
30
...
PCI_AD[31:24]
Section 13.2
Frequency,
illegal
44.33
33.25
MHz
66.5
4.29
4.16
...
22-7