SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 130

• Manufacturer Part Number: SAA7115HLBE
• Description: Video ICs ADV DGTL VIDEO DECODR
• Manufacturer: NXP Semiconductors

Specifications of SAA7115HLBE

• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-407
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Resolution: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7115HL/V1,557 SAF7115HLBE

PNX1300/01/02/11 Data Book
7.16.4
PNX1300 EVO features are enabled by setting the ap-
propriate fields of the EVO_CTL register shown in
Figure
Table
functionality replaces TM-1000 functions.
Table 7-9. EVO_CTL Register Fields
7-20
EVO_CTL EVO_ENABLE
Figure 7-30. EVO MMIO registers.
Register
MMIO_BASE
0x10 184C
0x10 1840
0x10 1844
0x10 1848
0x10 1850
7-9. If features are enabled, new PNX1300 the
offset:
7-30. The register fields are described in
EVO Control Register (EVO_CTL)
FULL_BLENDING
CLIPPING_ENABLE When set to 1, the values stored in EVO_CLIP are used for the clipping of output data. Otherwise,
SYNC_STREAMING When set to 1 in data-streaming mode, VO_IO2 generates a DATA_VALID signal. See
FIELD_SYNC
GENLOCK
KEY_ENABLE
EVO_CTL (r/w)
EVO_MASK (r/w)
EVO_CLIP (r/w)
EVO_KEY (r/w)
EVO_SLVDLY (r/w)
Field
PRELIMINARY SPECIFICATION
When set to 1, EVO features are enabled. When set to 0 (the hardware reset value), the EVO
behaves exactly like a TM-1000 VO unit. Default: 0.
Activates full 8-bit alpha blending when set to 1. When set to 0, only the original five TM-1000
blending levels are implemented (0%, 25%, 50%, 75%, 100%). Default: 0.
TM-1000 default values (240 and 16 for Y, U and V) are used. Default: 0.
7.18.2, “Data-transfer
When set, VO_IO2 will generate frame synchronization signal that follows the field number in
SAV/EAV codes (Field1 gives a low VO_IO2, Field2 gives a high VO_IO2). Default: 0.
Activates Genlock mode when set to 1 and VO_CTL. SYNC_MASTER = 0. Default: 0.
When set, this bit activates chroma key. The overlay values (Y, U and V) are compared to the val-
ues stored in the EVO_KEY register. Bits that correspond to bits set in MASK_Y and MASK_UV
are ignored for the comparison. When there is an exact match between the pixel value and the
value in EVO_KEY register (less the bits selected by MASK_Y and MASK_UV), then the overlay
value is not present in the output stream, resulting in full transparency.
The key is 24 bits (Y, U and V are 8 bits each). Default: 0.
31
MASK_Y
31
0
HIGHER_CLIPUV
0
RESERVED
RESERVED
0
1
27
MASK_UV
27
Modes”. Default: 0.
23
23
LOWER_CLIPUV
KEY_V
The hardware reset value of EVO_CTL register is
0x10000000, which means that EVO functions are dis-
abled on reset and must be enabled by software. The MS
four bits indicate the EVO revision number.
To ensure compatibility with future devices, any unde-
fined MMIO bits should be ignored when read, and writ-
ten as ‘0’s.
19
RESERVED
19
Description
15
15
HIGHER_CLIPY
KEY_Y
RESERVED
CLIPPING_ENABLE
FULL_BLENDING
SYNC_STREAMING
GENLOCK
11
11
Philips Semiconductors
SLAVE_DLY
FIELD_SYNC
KEY_ENABLE
7
7
EVO_ENABLE
LOWER_CLIPY
KEY_U
3
3
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