SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 189

• Manufacturer Part Number: SAA7115HLBE
• Description: Video ICs ADV DGTL VIDEO DECODR
• Manufacturer: NXP Semiconductors

Specifications of SAA7115HLBE

• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-407
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Resolution: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7115HL/V1,557 SAF7115HLBE

Philips Semiconductors
freshed every 64 ms or 2048 rows every 32 ms or one
row every 15.62 µsec. New SDRAM devices (i.e. 256
Mbit generation support an 8K refresh interval, therefore
one row every 7.81 µsec.
The MMI performs refresh at timed intervals: one CBR
refresh command must be issued every 15.6 µs or every
7.81 µsec. A counter in the MMI keeps track of the num-
ber of SDRAM clock cycles between refresh operations.
This counter starts after the CBR operation has complet-
ed; this CBR operation take 19 cycles. When the counter
reaches a programmed limit, the next refresh operation
is due, and the next-in-line data transfer request from the
data-highway is delayed until the CBR operation is exe-
cuted.
All devices in the main-memory system are refreshed si-
multaneously. The REFRESH field in the MM_CONFIG
register determines the number of memory-system clock
cycles (as distinguished from PNX1300 core clock cy-
cles) between the CBR refresh operations.
Each CBR refresh operation takes 19 SDRAM clock cy-
cles. Thus, at 100-MHz, refresh consumes about 1.2% of
maximum available SDRAM bandwidth (19 cycles out of
1560). The bandwidth impact is slightly lower at higher
frequencies.
Table 12-13
for typical SDRAM operation speeds with a 15.62 µs re-
fresh period. This number includes the worst case sce-
nario in order to guaranty the 15.62 µs refresh period.
Table 12-13. REFRESH value for a 15.62 µs period
Table 12-14
for typical SDRAM operation speeds with a 7.81 µs re-
fresh period.This number includes the worst case sce-
nario in order to guaranty the 7.81 µs refresh period.
Table 12-14. REFRESH value for a 7.81 µs period
SDRAM Operation Speed
SDRAM Operation Speed
100 MHz
125 MHz
133 MHz
143 MHz
166 MHz
183 MHz
100 MHz
125 MHz
133 MHz
143 MHz
166 MHz
183 MHz
lists the number of memory-system clocks
lists the number of memory-system clocks
Value For REFRESH Field
Value For REFRESH Field
(decimal, hexadecimal)
(decimal, hexadecimal)
2819, 0B03
1256, 04E9
1384, 05E6
1523, 05F3
1914, 0779
2038, 07F6
2195, 0892
2554, 09F9
1072, 0435
742, 02E6
936, 03A9
992, 03E7
12.12 POWER-DOWN MODE
When PNX1300 is put into power-down mode to reduce
power consumption, the MMI responds by putting the
SDRAM devices into their power-down mode. In this
mode, the SDRAM devices retain their contents through
self-refresh.
12.13 OUTPUT DRIVER CAPACITY
PNX1300’s output driver circuits for the memory address
and control signals (output signals in
drive up to two memory devices when the memory inter-
face is operating at 183 MHz. If more devices are con-
nected, then a lower SDRAM clock frequency must be
chosen.
Table 12-15
number of memory devices connected to unbuffered
memory interface signals.
Two identical outputs are provided for both the MM_CKE
(clock-enable) and MM_CLK signals. Each MM_CKE
and MM_CLK signal is capable of driving one SDRAM
devices at 183 MHz.
12.14 SIGNAL PROPAGATION DELAY
The PNX1300 MMI no longer has the two special pins,
MM_MATCHOUT and MM_MATCHIN, that were used in
the TM-1100 and TM-1000. This loop helped the inter-
face compensate for the propagation delay through cir-
cuit-board traces to and from the external SDRAM devic-
es. It is now integrated into the MMI. Read timing is
internally derived.
To avoid excessive ringing of the clock signals, series
termination with a 33-ohm resistor is advised at the clock
outputs.
The delay of the memory clock with respect to the inter-
nal sending and receiving clocks is adjusted inside the
memory interface to achieve reliable communication and
guarantee correct setup and hold times.
Figure 12-4
Two SDRAM devices share a single clock output. The
clock signals should have source-series termination.
12.15 CIRCUIT BOARD DESIGN
PNX1300 and its memory array form a high-speed digital
system. Even though only a small number of chips is in-
volved, this digital system operates at frequencies high
enough to make the analog characteristics of the con-
nections between the chips significant. Consequently,
the system designer must take care to ensure reliable
operation.
12.15.1 General Guidelines
• In general, PNX1300 and its memory chips must be
PRELIMINARY SPECIFICATION
as close together as possible to minimize parasitic
COMPENSATION
lists the clock frequency as a function of the
shows a conceptual circuit board layout.
SDRAM Memory System
Table
12-9), can
12-7