SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 402
![Video ICs ADV DGTL VIDEO DECODR](/photos/27/77/277797/qfp100_sml.jpg)
SAA7115HLBE
Manufacturer Part Number
SAA7115HLBE
Description
Video ICs ADV DGTL VIDEO DECODR
Manufacturer
NXP Semiconductors
Datasheet
1.SAA7115HLBE.pdf
(548 pages)
Specifications of SAA7115HLBE
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 70 C
Package / Case
SOT-407
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Number Of Channels
2
Resolution
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
SAA7115HL/V1,557 SAF7115HLBE
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Philips Semiconductors
Signed 16-bit load
pseudo-op for ild16d(0)
SYNTAX
FUNCTION
DESCRIPTION
argument. (Note: pseudo operations cannot be used in assembly source files.)
and stores the result in rdest. If the memory address contained in rsrc1 is not a multiple of 2, the result of
undefined but no exception will be raised. This load operation is performed as little-endian or big-endian depending on
the current setting of the bytesex bit in the PCSW.
defined only for 32-bit loads and stores.
modification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written and
the data cache status bits are updated if the addressed locations are cacheable. if the LSB of rguard is 0, rdest is not
changed and
EXAMPLES
r10 = 0xd00, [0xd00] = 0x22,
[0xd01] = 0x11
r30 = 0, r20 = 0xd04, [0xd04] = 0x84,
[0xd05] = 0x33
r40 = 1, r20 = 0xd04, [0xd04] = 0x84,
[0xd05] = 0x33
r50 = 0xd01
The
The
The result of an access by
The
[ IF rguard ] ild16 rsrc1 → rdest
if rguard then {
}
if PCSW.bytesex = LITTLE_ENDIAN then
else
temp<7:0> ← mem[(rsrc1 +(1 ⊕ bs)]
temp<15:8> ← mem[(rsrc1 + (0 ⊕ bs)]
rdest ← sign_ext16to32(temp<15:0>)
ild16
ild16
ild16
bs ← 1
bs ← 0
Initial Values
ild16
operation loads the 16-bit memory value from the address contained in rsrc1, sign extends it to 32 bits,
operation is a pseudo operation transformed by the scheduler into an
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
has no side effects whatever.
ild16
to the MMIO address aperture is undefined; access to the MMIO aperture is
ild16 r10 → r60
IF r30 ild16 r20 → r70
IF r40 ild16 r20 → r80
ild16 r50 → r90
Operation
PRELIMINARY SPECIFICATION
PNX1300/01/02/11 DSPCPU Operations
r60 ← 0x00002211
no change, since guard is false
r80 ← 0xffff8433
r90 undefined, since 0xd01 is not a multiple of 2
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
ild16d ild16r ild16x
ild16d(0)
ATTRIBUTES
Result
SEE ALSO
with the same
ild16
ild16
dmem
4, 5
No
—
6
1
3
A-104
is
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