SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 462

• Manufacturer Part Number: SAA7115HLBE
• Description: Video ICs ADV DGTL VIDEO DECODR
• Manufacturer: NXP Semiconductors

Specifications of SAA7115HLBE

• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-407
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Resolution: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7115HL/V1,557 SAF7115HLBE

Philips Semiconductors
32-bit store
pseudo-op for h_st32d(0)
SYNTAX
FUNCTION
DESCRIPTION
arguments. (Note: pseudo operations cannot be used in assembly files.)
value is an opcode modifier and must be a multiple of 4. This store operation is performed as little-endian or big-
endian depending on the current setting of the bytesex bit in the PCSW.
MSE (Misaligned Store Exception) bit in the PCSW register is set to 1. Additionally, if the TRPMSE (TRaP on
Misaligned Store Exception) bit in PCSW is 1, exception processing will be requested on the next interruptible jump.
memory operations is undefined). The state of the BSX bit in the PCSW has no effect on MMIO access by
modification of the addressed memory locations (and the modification of cache if the locations are cacheable). If the
LSB of rguard is 1, the store takes effect. If the LSB of rguard is 0, st32 has no side effects whatever; in particular, the
LRU and other status bits in the data cache are not affected.
EXAMPLES
r10 = 0xd00, r80 = 0x44332211
r50 = 0, r20 = 0xd01,
r70 = 0xaabbccdd
r60 = 1, r30 = 0xd04,
r70 = 0xaabbccdd
The
The
If
The
The
[ IF rguard ] st32 rsrc1 rsrc2
if rguard then {
}
st32
if PCSW.bytesex = LITTLE_ENDIAN then
else
mem[rsrc1 + (3 ⊕ bs)] ← rsrc2<7:0>
mem[rsrc1 + (2 ⊕ bs)] ← rsrc2<15:8>
mem[rsrc1 + (1 ⊕ bs)] ← rsrc2<23:16>
mem[rsrc1 + (0 ⊕ bs)] ← rsrc2<31:24>
st32
st32
st32
st32
bs ← 3
bs ← 0
is misaligned (the memory address in rsrc1 is not a multiple of 4), the result of
Initial Values
operation can be used to access the MMIO address aperture (the result of MMIO access by 8- or 16-bit
operation stores all 32 bits of rsrc2 into the memory locations pointed to by the address in rsrc1. The d
operation is a pseudo operation transformed by the scheduler into an
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
st32 r10 r80
IF r50 st32 r20 r70
IF r60 st32 r30 r70
Operation
PRELIMINARY SPECIFICATION
PNX1300/01/02/11 DSPCPU Operations
[0xd00] ← 0x44, [0xd01] ← 0x33,
[0xd02] ← 0x22, [0xd03] ← 0x11
no change, since guard is false
[0xd04] ← 0xaa, [0xd05] ← 0xbb,
[0xd06] ← 0xcc, [0xd07] ← 0xdd
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
h_st32d st32d st16 st16d
h_st32d(0)
st32
ATTRIBUTES
SEE ALSO
Result
st8 st8d
is undefined, and the
with the same
st32
st32
dmem
4, 5
n/a
No
31
—
2
A-164
.