MT46H8M32LFB5-6 IT:H Micron Technology Inc, MT46H8M32LFB5-6 IT:H Datasheet - Page 68

DRAM Chip DDR SDRAM 256M-Bit 8Mx32 1.8V 90-Pin VFBGA Tray

MT46H8M32LFB5-6 IT:H

Manufacturer Part Number
MT46H8M32LFB5-6 IT:H
Description
DRAM Chip DDR SDRAM 256M-Bit 8Mx32 1.8V 90-Pin VFBGA Tray
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet

Specifications of MT46H8M32LFB5-6 IT:H

Density
256 Mb
Maximum Clock Rate
166 MHz
Package
90VFBGA
Address Bus Width
14 Bit
Operating Supply Voltage
1.8 V
Maximum Random Access Time
6.5|5 ns
Operating Temperature
-40 to 85 °C
Organization
8Mx32
Address Bus
14b
Access Time (max)
6.5/5ns
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
1.95V
Operating Supply Voltage (min)
1.7V
Supply Current
120mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Compliant
Figure 31: Data Output Timing –
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN
All DQ values, collectively
Command
DQS or LDQS/UDQS
CK#
CK
READ
T0
Notes:
3
2
1. Commands other than NOP can be valid during this cycle.
2. DQ transitioning after DQS transitions define
3. All DQ must transition by
4.
NOP
T1
t
AC is the DQ output window relative to CK and is the long-term component of DQ skew.
CL = 3
1
t
LZ
t
AC and
NOP
T2
t
t
RPRE
DQSCK
t
1
t
DQSCK
LZ
t
AC
T2n
4
T2
t
68
DQSQ after DQS transitions, regardless of
NOP
T3
256Mb: x16, x32 Mobile LPDDR SDRAM
1
T2n
T3n
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
DQSCK
t
AC
T3
NOP
4
T4
t
1
DQSQ window.
T3n
T4n
T4
NOP
T5
1
©2008 Micron Technology, Inc. All rights reserved.
T4n
T5n
READ Operation
t
AC.
T5
NOP
T6
1
Don’t Care
T5n
t
t
t
HZ
HZ
RPST

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