MT46H8M32LFB5-6 IT:H Micron Technology Inc, MT46H8M32LFB5-6 IT:H Datasheet - Page 76

• Manufacturer Part Number: MT46H8M32LFB5-6 IT:H
• Description: DRAM Chip DDR SDRAM 256M-Bit 8Mx32 1.8V 90-Pin VFBGA Tray
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H8M32LFB5-6 IT:H

• Density: 256 Mb
• Maximum Clock Rate: 166 MHz
• Package: 90VFBGA
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 1.8 V
• Maximum Random Access Time: 6.5|5 ns
• Operating Temperature: -40 to 85 °C
• Organization: 8Mx32
• Address Bus: 14b
• Access Time (max): 6.5/5ns
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 120mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Figure 39: WRITE-to-READ – Interrupting
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN
Command
Address
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
DQ
DQ
DQ
CK#
DM
DM
DM
CK
4
5
4
5
4
5
WRITE
Bank a,
Col b
T0
Notes:
t
t
t
1,2
DQSS
DQSS
DQSS
1. An interrupted burst of 4 is shown; 2 data elements are written.
2. A10 is LOW with the WRITE command (auto precharge is disabled).
3.
4. DQS is required at T2 and T2n (nominal case) to register DM.
5. D
D
IN
t
NOP
WTR is referenced from the first positive CK edge after the last data-in pair.
D
T1
IN
IN
b = data-in for column b; D
D
D
IN
IN
T1n
D
IN
D
IN
NOP
T2
t
WTR
T2n
3
76
Bank a,
READ
Col n
T3
OUT
256Mb: x16, x32 Mobile LPDDR SDRAM
n = data-out for column n.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
NOP
T4
Don’t Care
CL = 3
CL = 3
CL = 3
T5
NOP
©2008 Micron Technology, Inc. All rights reserved.
WRITE Operation
T5n
Transitioning Data
D
D
D
OUT
OUT
OUT
T6
NOP
D
D
D
OUT
OUT
OUT
T6n