MT46H8M32LFB5-6 IT:H Micron Technology Inc, MT46H8M32LFB5-6 IT:H Datasheet - Page 95

• Manufacturer Part Number: MT46H8M32LFB5-6 IT:H
• Description: DRAM Chip DDR SDRAM 256M-Bit 8Mx32 1.8V 90-Pin VFBGA Tray
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H8M32LFB5-6 IT:H

• Density: 256 Mb
• Maximum Clock Rate: 166 MHz
• Package: 90VFBGA
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 1.8 V
• Maximum Random Access Time: 6.5|5 ns
• Operating Temperature: -40 to 85 °C
• Organization: 8Mx32
• Address Bus: 14b
• Access Time (max): 6.5/5ns
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 120mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Revision History for Commands, Operations, and Timing Diagrams
Update – 01/09
Update – 07/08
Update – 05/08
Update – 03/08
Update – 12/07
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN
• Initialization: Updated item 1 relative to CKE.
• SELF REFRESH Command section: Updated description.
• Truth Tables (Current State Bank n – Command to Bank n and Current State Bank n –
• Self Refresh: Updated description.
• Truth Table, Current State Bank n – Command to Bank m: Corrected note 3b,
• Auto Precharge: Added third paragraph regading
• Bank Write – Without Auto Precharge: Corrected note 4.
• Functional Description, Burst Definition table, Extended Mode Register, and through-
• Output Drive Strength: Added three-quarter drive strength and deleted one-eighth
• Extended Mode Register Figure: Expanded driver strength section to include three-
• Updated note 2 for the following figures:
• Updated note 3 for the following figures:
• Removed final note for the following figures:
• Figure 43, WRITE-to-PRECHARGE – Odd Number of Data, Interrupting: Extended
• Concurrent Auto Precharge: Updated figure references.
• Figure 19, Extended Mode Register: Updated to include mid-strength driver informa-
Command to Bank m): Clarified note 1.
changed "disabled" to "enabled."
out document as appropriate: Added BL 16.
drive strength; added 37 ohm (deleted 100 ohm).
quarter drive strength.
– Consecutive READ Bursts
– Nonconsecutive READ Bursts
– Random READ Accesses
– Terminating a READ Burst
– READ-to-PRECHARGE
– READ-to-WRITE
– Random WRITE Cycles
– WRITE-to-READ
– WRITE-to-READ – Odd Number of Data, Interrupting
– WRITE-to-PRECHARGE – Interrupting
t
tion.
WR to coincide with T5 transition.
95
256Mb: x16, x32 Mobile LPDDR SDRAM
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
RAS lock-out.
©2008 Micron Technology, Inc. All rights reserved.
Revision History