HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 100

• Manufacturer Part Number: HFIXF1110CC.B2 Q E000
• Manufacturer: Intel

Specifications of HFIXF1110CC.B2 Q E000

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Intel
6.3.2
07-Oct-2005
100
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
6.3.1.3.2
Use the TX FIFO drain when the link is down. The following is a step-by-step sequence to put a
port(s) into the TX FIFO drain mode:
6.3.1.3.3
To exit the TX FIFO drain mode.
The IXF1110 MAC RX FIFOs are provisioned so that each port has its own 17.0 KB memory
space. This is enough memory to ensure against an over-run on any port while transferring normal
Ethernet frame-size data.
The RX FIFOs are configured by default to automatically generate Pause control frames to initiate
the following:
Pause control frame generation is enabled by default in the
Section 8.5.5, “Global RX Block Register Overview” on page 154
to set the RX FIFO watermarks.
RX FIFO
1. The system detects that link is down for a given port using bits 21:20 of the RX Config Word
2. Set the appropriate bit to 1 for the given port in the TX FIFO Drain Register ($0x620) once
3. Set the MAC Soft Reset Register bit to 1 for the port(s) that has entered the TX FIFO drain
4. De-assert the MAC Soft Reset Register. Redo the MAC configurations. If applicable, re-
5. The connected SPI4-2 NPU or ASIC can now dump data to the port(s) that has entered the
6. Monitor the RX Config Word Register to reestablish link with the link partner. Exit the TX
1. Set the TX FIFO Drain Register bits back to 0. This exits the TX FIFO drain mode and the
2. The IXF1110 is ready to resume normal data transmission.
•
•
Register ($Port_Index + 0x16). The SPI4-2 TX FIFO port status is SATISFIED when the link
is down.
link is down. This incurs the following:
mode.
enable auto-negotiation for the selected port(s) by setting bit 5 of the Diverse Config Register
back to 1.
drain mode. All data sent to the port(s) selected is discarded and not recorded in any register in
the IXF1110.
FIFO drain mode when the system software detects link establishment.
TX FIFO status bus now indicates the actual TX FIFO status.
Halt the link partner when the RX FIFO High Watermark is reached
Restart the link partner when the data stored in the RXFIFO falls below the Low Watermark.
b. Causes the TX FIFO for the selected port to enter a reset state
a. Enables the drain mode
c. Causes the TX FIFO SPI4-2 FIFO status for that port to change to STARVING.
Intel
Putting the TX FIFO in Drain Mode
Exiting the TX FIFO Drain Mode
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Order Number: 250210, Revision: 009
“FC Enable ($ Port_Index +
documents the registers needed
0x12)”.
Datasheet