HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 139

• Manufacturer Part Number: HFIXF1110CC.B2 Q E000
• Manufacturer: Intel

Specifications of HFIXF1110CC.B2 Q E000

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Datasheet
Table 74. RX Packet Filter Control ($ Port_Index + 0x19) (Sheet 1 of 2)
Register Description: This register allows for specific packet types to be marked for filtering,
and is used in conjunction with the RX FIFO Errored Frames Drop Enable Register
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
2. Jumbo frames (1519 - 9600 bytes), matching the filter conditions, which would cause the frame to be
3. Frames are dropped only when the appropriate bits are set in the RX FIFO Errored Frame Drop Enable
31:6
Bit
5
4
3
dropped by the RX FIFO, will not be dropped. Instead, jumbo frames that are marked to be dropped by the
RX FIFO, based on the filter setting in this register, will still be sent across the SPI4-2 interface, but will be
marked as an EOP abort frame. Thus, jumbo frames matching the filter conditions will not be counted in the
RX FIFO Number of Frames Removed Register because they are not removed by the RX FIFO. Only
standard packet sizes (64 - 1518 bytes) meeting the filter conditions set in this register will actually be
dropped by the RX FIFO and counted in the RX FIFO Number of Frames Removed.
Register
SPI4-2 interface and marked as EOP abort frames.
Reserved
CRC Error Pass
Pause Frame
Pass
VLAN Drop En
Intel
(Table 92 on page
®
Name
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
2
2
Order Number: 250210, Revision: 009
160). When the appropriate bits are not set, the frames are sent across the
Reserved
This bit enables a Global filter on frames with a CRC
Error.
When CRCErrorPASS = 0, all frames with a CRC
Error are marked as bad.
NOTE: When used in conjunction with the RX FIFO
ErroredFrameDropEnable[9:0] Register (see
on page
the RX FIFO. Otherwise, the frame is sent across the
SPI4-2 interface but marked as an EOP Abort frame.
When the CRC Error Pass Filter bit = 0, it takes
precedence over the other filter bits. Any packet
regardless if it is a Pause, Unicast, Multicast or
Broadcast packet with a CRC error will be marked as
bad frames when CRC Error Pass = 0
When CRCErrorPASS = 1, frames with a CRC Error
are not marked as bad and are passed to the SPI4-2
interface for transfer as good frames, regardless of
the state of the FrameDropEn[9:0] bits.
This bit enables a Global filter on Pause frames.
When PauseFramePass = 0, all Pause frames are
marked as bad.
NOTE: When used in conjunction with the RX FIFO
ErroredFrameDropEnable[9:0] Register (see
on page
the RX FIFO. Otherwise, the frame is sent across the
SPI4-2 interface but marked as an EOP Abort frame.
NOTE: When PauseFramePass = 1, all Pause
This bit enables a Global filter on VLAN frames.
When VLANDropEn = 0, all VLAN frames are passed
to the SPI4-2 Interface.
When VLANDropEn = 1, all VLAN frames are
dropped.
Intel
frames are not marked as bad and are
passed to the SPI4-2 interface for transfer as
good frames, regardless of the state of the
FrameDropEn[9:0] bits.
160). This allows the frame to be dropped in
160). This allows the frame to be dropped in
3
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Description
Table 92
Table 92
Type
R/W
R/W
R/W
R
1
0x00000000
07-Oct-2005
0x000000
Default
0
0
0
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