HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 58

• Manufacturer Part Number: HFIXF1110CC.B2 Q E000
• Manufacturer: Intel

Specifications of HFIXF1110CC.B2 Q E000

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Intel
5.2
07-Oct-2005
58
®
Figure 9. SPI4-2 Interfacing with the Network Processor or Forwarding Engine
Table 17. SPI4-2 Interface Signal Summary (Sheet 1 of 2)
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
System Packet Interface Level 4 Phase 2
The System Packet Interface Level 4 Phase 2 (SPI4-2) provides a high-speed connection to a
network processor or an ASIC. The interface implemented on the IXF1110 operates at data rates up
to 12.8 Gbps and supports up to ten 1 Gbps MAC ports. The data path is 16 lanes wide in each
direction, with each lane operating from 640 Mbps up to 800 Mbps. Port addressing, start/end
packet control, and error control codes are all transferred “in-band” on the data bus. In-band
addressing supports up to 10 ports. Separate transmit and receive FIFO status lines are used for
flow control. By keeping the FIFO status information out-of-band, the transmit and receive
interfaces may be de-coupled to operate independently.
of the IXF1110 SPI4-2 interface.
TDAT[15:0]_P/N
TDCLK_P/N
TCTL_P/N
Signal Name
IXF1110
Intel
Intel
MAC
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
®
RDAT[15:0]_P/N
TDAT[15:0]_P/N
RDCLK_P/N
TDCLK_P/N
RSTAT[1:0]
TSTAT[1:0]
Transmit Data Bus: Differential LVDS lines used to carry payload data and in-band
control words.
Internally terminated differentially with 100
Transmit Data Clock: Differential LVDS clock associated with TDAT[15:0] and TCTL.
Data and control lines are driven off the rising and falling edges of the clock.
Internally terminated differentially with 100
NOTE: If TDCLK is applied to the IXF1110 MAC after the device has come out of
reset, the system designer must ensure the TDCLK is stable when applied. Failure to
due so can result in the IXF1110 MAC training on a non-stable clock, causing DIP4
errors and data corruption.
Transmit Control: Differential LVDS lines used to indicate when a control word is
being transmitted. A High level indicates a control word present on TDAT[15:0].
Internally terminated differentially with 100
RCTL_P/N
TCTL_P/N
Order Number: 250210, Revision: 009
RSCLK
TSCLK
Receive
Control
Transmit
Control
Data
Data
Signals
SPI-4.2
Transmit
FIFO Status/
Flow Control
FIFO Status/
Flow Control
Transmit
Signal Description
Receive
Figure 9
and
TSCLK
TSTAT[1:0]
TDCLK_P/N
TDAT[15:0]_P/N
TCTL_P/N
RSCLK
RSTAT[1:0]
RDCLK_P/N
RDAT[15:0]_P/N
RCTL_P/N
Table 17
or Forwarding Engine
with SPI4-2 Interface
Network Processor
provide an overview
Datasheet
B3432-01