HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 125
HFIXF1110CC.B2 Q E000
Manufacturer Part Number
HFIXF1110CC.B2 Q E000
Description
Manufacturer
Intel
Datasheet
1.HFIXF1110CC.B2_Q_E000.pdf
(183 pages)
Specifications of HFIXF1110CC.B2 Q E000
Number Of Transceivers
1
Screening Level
Commercial
Mounting
Surface Mount
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Lead Free Status / RoHS Status
Not Compliant
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8.4
8.5
Datasheet
Figure 43. Register Overview
Table 51. MAC Control Register Map (Sheet 1 of 2)
Note: All registers in the IXF1110MAC are 32 bits.
Per Port Registers
The following section covers all of the registers that are replicated in each of the 10 ports in the
IXF1110 MAC. These registers perform an identical function in each port.
The address vector for the IXF1110 MAC is 11 bits wide. This allows for 7 bits of port-specific
access and a 4-bit vector to address each port and all global registers. The address format is shown
in
Memory Map
Table 51
global control and status registers are used to configure or report on all ports, and some registers
are replicated on a per-port basis.
“Station Address Low ($ Port_Index + 0x00)”
“Station Address High ($ Port_Index + 0x01)”
Reserved
“FDFC Type ($ Port_Index + 0x03)”
Reserved
Reserved
Reserved
“FC TX Timer Value ($ Port_Index + 0x07)”
“FDFC Address Low ($ Port_Index + 0x08)”
“FDFC Address High ($ Port_Index + 0x09)”
Reserved
Reserved
“IPG Transmit Time ($ Port_Index + 0x0C)”
Reserved
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
Figure
10
through
43.
Intel
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Port Select & Global Registers
Table 59 on page 132
Order Number: 250210, Revision: 009
Register
MAC Control Registers (Port Index + Offset)
Intel
®
provide theIXF1110 MAC memory maps. A number of
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
6
Bit Size
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Per-Port Registers
Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
R
R
R
1
Page
Ref
133
133
133
133
134
134
134
--
–
–
–
–
–
–
07-Oct-2005
Offset
Ox0B
0X06
0x0A
0x0C
0x0D
0x00
0x01
0x02
0x03
0x04
0x05
0x07
0x08
0x09
0
125
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