HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 151

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HFIXF1110CC.B2 Q E000

Manufacturer Part Number
HFIXF1110CC.B2 Q E000
Description
Manufacturer
Intel
Datasheet

Specifications of HFIXF1110CC.B2 Q E000

Number Of Transceivers
1
Screening Level
Commercial
Mounting
Surface Mount
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Lead Free Status / RoHS Status
Not Compliant
Datasheet
Table 82. MAC Soft Reset ($ 0x505)
Table 83. CPU Interface ($ 0x508)
Register Description: Per-port software activated reset of the MAC core.
Register Description: CPU interface Endian select. This register allows the user to select the
Endian of the CPU interface to allow various different CPUs to be connected to the IXF1110.
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
31:10
Bit
9
8
7
6
5
4
3
2
1
0
31:1
Bit
0
Intel
Reserved
MAC Soft Reset Port 9
MAC Soft Reset Port 8
MAC Soft Reset Port 7
MAC Soft Reset Port 6
MAC Soft Reset Port 5
MAC Soft Reset Port 4
MAC Soft Reset Port 3
MAC Soft Reset Port 2
MAC Soft Reset Port 1
MAC Soft Reset Port 0
Reserved
Endian
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Name
Name
Order Number: 250210, Revision: 009
Reserved
0 = Little Endian
1 = Big Endian
Intel
Reserved
Port 9
0 = Reset inactive
1 = Reset active
Port 8
0 = Reset inactive
1 = Reset active
Port 7
0 = Reset inactive
1 = Reset active
Port 6
0 = Reset inactive
1 = Reset active
Port 5
0 = Reset inactive
1 = Reset active
Port 4
0 = Reset inactive
1 = Reset active
Port 3
0 = Reset inactive
1 = Reset active
Port 2
0 = Reset inactive
1 = Reset active
Port 1
0 = Reset inactive
1 = Reset active
Port 0
0 = Reset inactive
1 = Reset active
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Description
Description
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Type
R/W
1
R
1
0x00000000
0x00000000
0x00000000
07-Oct-2005
0x00000
Default
Default
0
0
0
0
0
0
0
0
0
0
0
151

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