HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 91

• Manufacturer Part Number: HFIXF1110CC.B2 Q E000
• Manufacturer: Intel

Specifications of HFIXF1110CC.B2 Q E000

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

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5.6.2.2
Datasheet
Figure 24. Read Timing – Asynchronous Interface
Figure 25. Write Timing – Asynchronous Interface
Write Access
The IXF1110 MAC Write access cycle operation is done in the following order:
Figure 25
UPX_DATA[31:0]
1. Chip Select (UPX_CS_L) is asserted at all times for the duration of the operation. The address
2. UPX_WR_L should be asserted by the CPU. The IXF1110 MAC latches the address.
3. The CPU drives valid data onto the processor bus (UPX_DATA[31:0]).
4. The CPU de-asserts the asynchronous Write signal (UPX_WR_L) of the IXF1110 MAC. The
5. The IXF1110 MAC assertss asynchronous-ready (UPX_RDY_L). The glue logic indicates to
UPX_DATA[31:0]
UPX_ADD[10:0]
UPX_ADD[10:0]
to be read should be on the IXF1110 MAC address bus (UPX_ADD[10:0]).
IXF1110 MAC latcheses the data.
the CPU that the Write cycle is complete.
UPX_RDY_L
UPX_RDY_L
UPX_RD_L
UPX_CS_L
UPX_WR_L
UPX_CS_L
provides the timing of the asynchronous interface for Write access.
Intel
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Order Number: 250210, Revision: 009
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IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
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07-Oct-2005
B3381-01
B3382-01
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