HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 47

• Manufacturer Part Number: HFIXF1110CC.B2 Q E000
• Manufacturer: Intel

Specifications of HFIXF1110CC.B2 Q E000

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

5.1.3
5.1.3.1
Datasheet
Table 14. CRC Errored Packets Drop Enable Behavior
Flow Control
Flow Control is an IEEE 802.3x-defined mechanism for one network node to request that its link
partner take a temporary “Pause” in packet transmission. This allows the requesting network node
to prevent FIFO overruns and dropped packets, by managing incoming traffic to fit its available
memory. The temporary pause allows the device to process packets already received or in transit,
thus freeing up the FIFO space allocated to those packets.
The IXF1110 MAC implements the IEEE 802.3x standard RX FIFO threshold-based Flow Control.
When appropriately programmed, the MAC can both generate and respond to IEEE standard pause
frames. The IXF1110 MAC also supports externally triggered flow control through the Transmit
Pause Control interface.
802.3x Flow Control (Full-Duplex Operation)
The IEEE 802.3x standard identifies four options related to system flow control:
The IXF1110 MAC supports all four options on a per-port basis. Bits 1:0 of the
Port_Index + 0x12)” on page 136
control in each direction independently.
The IEEE 802.3x flow control mechanism is accomplished within the MAC sublayer, and is based
on RX FIFO thresholds called watermarks. The RX FIFO level rises and falls as packets are
received and processed. When the RX FIFO reaches a watermark (either exceeding a High or
dropping below a Low after exceeding a High), the IXF1110 MAC control sublayer signals an
internal state machine to transmit a PAUSE frame. The FIFOs automatically generate PAUSE
frames (also called control frames) to initiate the following:
Figure 5
CRC Errored PASS
•
•
•
•
•
•
No Pause
Symmetric Pause (both directions)
Asymmetric Pause (Receive direction only)
Asymmetric Pause (Transmit direction only)
Halt the link partner when the High watermark is reached.
Restart the link partner when the data stored in the FIFO falls below the Low watermark.
illustrates the IEEE 802.3 FIFO flow control functions.
1
0
1
0
Intel
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Frame Drop En
Order Number: 250210, Revision: 009
0
0
1
1
provide programmable control for enabling or disabling flow
Intel
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Packets are passed to the SPI4-2 interface. They are not
marked as bad and are sent to the switch or Network
Processor.
Packets are marked as bad but not dropped in the RX FIFO.
These packets are sent to the SPI4-2 interface, but with an
EOP Abort code to the switch or Network Processor.
Packets are not marked as bad and are sent to the switch or
Network Processor regardless of the Frame Drop En setting.
CRC errored packets are marked as bad, dropped in the RX
FIFO, and never appear at the SPI4-2 interface.
Actions
“FC Enable ($
07-Oct-2005
47