HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 8

• Manufacturer Part Number: HFIXF1110CC.B2 Q E000
• Manufacturer: Intel

Specifications of HFIXF1110CC.B2 Q E000

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Intel
07-Oct-2005
8
25 Mode 1 Clock Cycle to Data Bit Relationship ............................................................................. 86
26 LED Data Decodes ..................................................................................................................... 87
27
28 CPU Interface Signals ................................................................................................................ 89
29 Recommended JTAG Termination ............................................................................................. 92
30 Supported Boundary Scan Instructions ...................................................................................... 93
31 Power Sequencing ..................................................................................................................... 97
32 Analog Power Balls .................................................................................................................... 97
33 SFP-to-IXF1110 Connection .................................................................................................... 104
34 Absolute Maximum Ratings ...................................................................................................... 106
35 Operating Conditions ............................................................................................................... 107
36 2.5 V LVTTL and CMOS I/O Electrical Characteristics ............................................................ 108
37 LVDS I/O Electrical Characteristics .......................................................................................... 108
38 Undershoot/Overshoot Limits ................................................................................................... 109
39 CPU Timing Parameters........................................................................................................... 110
40 JTAG Timing Parameters ......................................................................................................... 112
41 Transmit Pause Control Interface Parameters ......................................................................... 113
42 Optical Module Interrupt Timing Parameters ............................................................................ 114
43 I
44 Hardware Reset Timing Parameters ........................................................................................ 117
45 LED Timing Parameters ........................................................................................................... 118
46 Transmitter Characteristics....................................................................................................... 119
47 Receiver Characteristics........................................................................................................... 120
48 SPI4-2 Transmit FIFO Status Bus Timing Parameters............................................................. 121
49 SPI4-2 Receive FIFO Status Bus Timing Parameters.............................................................. 122
50 SPI4-2 LVDS Rise/Fall Times .................................................................................................. 122
51 MAC Control Register Map....................................................................................................... 125
52 MAC RX Statistics Register Map .............................................................................................. 126
53 MAC TX Statistics Register Map .............................................................................................. 127
54 Global Status and Configuration Register Map ........................................................................ 128
55 RX Block Register Map ............................................................................................................ 129
56 TX Block Register Map ............................................................................................................. 130
57 SPI4-2 Block Register Map ...................................................................................................... 131
58 SerDes Block Register Map .................................................................................................... 131
59 Optical Module Interface Block Register Map ......................................................................... 132
60 Station Address Low ($ Port_Index + 0x00) ............................................................................. 133
61 Station Address High ($ Port_Index + 0x01) ............................................................................ 133
62 FDFC Type ($ Port_Index + 0x03) ........................................................................................... 133
63 FC TX Timer Value ($ Port_Index + 0x07) ............................................................................... 133
64 FDFC Address Low ($ Port_Index + 0x08)............................................................................... 134
65 FDFC Address High ($ Port_Index + 0x09).............................................................................. 134
66 IPG Transmit Time ($ Port_Index + 0x0C) ............................................................................... 134
67 Pause Threshold ($ Port_Index + 0x0E) .................................................................................. 135
68 Max Frame Size ($ Port_Index + 0x0F).................................................................................... 135
69 FC Enable ($ Port_Index + 0x12) ............................................................................................. 136
70 Discard Unknown Control Frame ($ Port_Index + 0x15).......................................................... 136
71 RX Config Word ($ Port_Index + 0x16) ................................................................................... 136
72 TX Config Word ($ Port_Index + 0x17) .................................................................................... 137
73 Diverse Config ($ Port_Index + 0x18) ..................................................................................... 138
74 RX Packet Filter Control ($ Port_Index + 0x19) ....................................................................... 139
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
LED Behavior............................................................................................................................. 88
2
C AC Timing Characteristics .................................................................................................. 115
Intel
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Order Number: 250210, Revision: 009
Datasheet