HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 28

no-image

HFIXF1110CC.B2 Q E000

Manufacturer Part Number
HFIXF1110CC.B2 Q E000
Description
Manufacturer
Intel
Datasheet

Specifications of HFIXF1110CC.B2 Q E000

Number Of Transceivers
1
Screening Level
Commercial
Mounting
Surface Mount
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Lead Free Status / RoHS Status
Not Compliant
Intel
07-Oct-2005
28
®
Table 7.
Table 8.
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
JTAG Interface Signal Descriptions
System Interface Signal Descriptions
TCK
TMS
TDI
TRST_L
TDO
CLK125
CLK50
SYS_RES_L
Signal Name
Signal Name
Intel
®
IIXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
AA24
T16
AC18
N18
Y24
AA5
C21
Y4
Order Number: 250210, Revision: 009
Ball Designator
Ball Designator
Input
Input
Input
Input
Output
Input
Input
Input
Type
Type
3.3 V
LVTTL
3.3 V
LVTTL
3.3 V
LVTTL
3.3 V
LVTTL
3.3 V
LVTTL
2.5 V
CMOS
2.5 V
CMOS
2.5 V
CMOS
Standard
Standard
JTAG Test Clock: Reference
clock for JTAG.
JTAG Test Mode Select: Selects
test mode for JTAG.
JTAG Test Data Input: Test data
sampled with respect to the rising
edge of TCK.
JTAG Test Reset: Reset input for
JTAG test.
JTAG Test Data Output: Test
data driven with respect to the
falling edge of TCK.
125 MHz Reference Clock: Input
clock to PLL.
SPI4-2 Reference Clock: Input
clock to SPI4-2 RX PLL.
Input range is 40 MHz to 50 MHz.
This clock multiplied by eight must
equal the required RX SPI4-2
data clock frequency.
System Reset: System hard
reset (active Low).
Signal Description
Signal Description
Datasheet

Related parts for HFIXF1110CC.B2 Q E000