HFIXF1110CC.B2 Q E000 Intel, HFIXF1110CC.B2 Q E000 Datasheet - Page 78

• Manufacturer Part Number: HFIXF1110CC.B2 Q E000
• Manufacturer: Intel

Specifications of HFIXF1110CC.B2 Q E000

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Intel
07-Oct-2005
78
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
5.4.4.1.1
The following sequence provides an example of reading the data stored in the Optical Module
Register 0x000 for Port 5:
5.4.4.1.2
The following sequence provides an example of writing data to the Optical Module Register 0xFF
for Port 9:
1. Program the
2. When this register is written and the I
3. The state machine uses the data in the Device ID and Register Address fields to build the data
4. The I
5. The I
6. The data is read through the CPU interface. The CPU must poll the Read Data Valid bit until it
1. Program the
All other bits in this register should be written with the value ‘0’.
This data is written into the I
All other bits in this register should be written with the value ‘0’.
This data is written into the I
examines the Port Address Select and enables the I
frame to be sent to the optical module.
actual data between the IXF1110 and the selected optical module (refer to the details in
Section 5.4.4.2, “I
Read_Data field, bits [7:0] of the I
the I
is set to ‘1. Only once this bit is set, it is safe to read the data in the I
b. Set the port to be accessed by setting bits [19:16] to 0x5.
d. Set the Device ID, bits [14:11] to be 0xA (Atmel compatible).
b. Set the port to be accessed by setting bits [19:16] to 0x9.
d. Set the Device ID, bits [14:11] to be 0xA (Atmel compatible).
a. Enable I
c. Select a READ access by setting bit 15 to ‘1’.
e. Set the 11-bit Register Address, bits [10:0] to 0x000.
a. Enable I
c. Select a WRITE access by setting bit 15 to ‘0’.
e. Set the 11-bit Register Address, bits [10:0] to 0xFF.
f. Initiate the I
f. Initiate the I
2
2
2
C Control Register to ‘1’ to signify that the Read data is valid.
C DATA_READ_FSM internal state machine takes over the task of transferring the
C DATA_READ_FSM internal state machine places the received data into the
Intel
Read Access Operation Example
Write Access Operation Example
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
“I
2
“I
2
C Block by setting bit 25 to ‘1’.
C Block by setting bit 25 to ‘1’.
2
2
C Control Ports 0-9 ($ 0x79B)” on page 177
C Control Ports 0-9 ($ 0x79B)”
2
2
C transfer by setting bit 24 to ‘1’.
C transfer by setting bit 24 to ‘1’.
2
C Protocol Specifics” on page
Order Number: 250210, Revision: 009
2
2
C Control Register in a single cycle via the CPU interface.
C Control Register in a single cycle via the CPU interface.
2
C Data Register, and sets the Read Data Valid bit, bit 20 of
2
C Start bit is at a Logic 1, the I
with the following information:
79).
2
C_DATA_0:9 output for the selected port.
with the following information:
2
C Data Register.
2
C access state machine
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