AM79C973BKC\W AMD (ADVANCED MICRO DEVICES), AM79C973BKC\W Datasheet - Page 105

• Manufacturer Part Number: AM79C973BKC\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC\W

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3/3.135V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Not Compliant

Note: The setting of MPPLBA or EMPPLBA only ef-
fects the address detection of the Magic Packet frame.
The Magic Packet’s data sequence must be made up
of 16 consecutive copies of the device’s physical ad-
dress (PADR[47:0]), regardless of what kind of destina-
tion address it has.
Th e r e a r e t wo g e n er a l m e th o d s t o p l a c e t h e
Am79C973/Am79C975 controller into the Magic
Packet mode. The first is the software method. In this
method, either the BIOS or other software, sets the
MPMODE bit (CSR5, bit 1). Then Am79C973/
Am79C975 controller must be put into suspend mode
(see description of CSR5, bit 0), allowing any current
network activity to finish. Finally, either PG must be
BCR Bit Number 15
Pattern Match
RAM Address
J+m
2+n
63
0
1
2
J
39
Data Byte 4m+3 Data Byte 4m+2 Data Byte 4m+1 Data Byte 4m+0 Pattern Control End Pattern P
Data Byte 4n+3
Data Byte 3
Data Byte 3
P3 pointer
P7 pointer
PMR_B4
32 31
BCR 47
8
7
Date Byte 4n+2
Data Byte 2
Data Byte 2
P2 pointer
P6 pointer
PMR_B3
Figure 50. Pattern Match RAM
P R E L I M I N A R Y
Pattern Match RAM Bit Number
24
Am79C973/Am79C975
0 15
Data Byte 4n+1
23
Data Byte 1
P1 pointer
P5 pointer
Data Byte1
PMR_B2
deasserted (hardware control) or MPEN (CSR5, bit 2)
must be set to 1 (software control).
Note: FASTSPNDE (CSR7, bit 15) has no meaning in
Magic Packet mode.
The second method is the hardware method. In this
method, the MPPEN bit (CSR116, bit 4) is set at power
up by the loading of the EEPROM. This bit can also be
set by software. The Am79C973/Am79C975 controller
will be placed in the Magic Packet Mode when either
the PG input is deasserted or the MPEN bit is set.
WUMI output will be asserted when the Am79C973/
Am79C975 controller is in the Magic Packet mode.
Magic Packet mode can be disabled at any time by as-
serting PG or clearing MPEN bit.
BCR 46
16
8
Data Byte 4n+0
7
15
Data Byte 0
Data Byte 0
P0 pointer
P4 pointer
PMR_B1
7
EOP
6
8
0 15
5
SKIP
7
Pattern Control
Pattern Control End Pattern P
Pattern Control
Pattern Enable
PMR_B0
BCR 45
4
bits
X
3
2
0
8
MASK
1
First Address
Last Address
Start Pattern
Start Pattern
21510D-55
Comments
Address
Second
0
P
P
1
k
105
1
k