AM79C973BKC\W AMD (ADVANCED MICRO DEVICES), AM79C973BKC\W Datasheet - Page 35

• Manufacturer Part Number: AM79C973BKC\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC\W

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3/3.135V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Not Compliant

group error. TX_ER is unused and is reserved for future
use and will always be driven to a logical zero.
Note: The TX_ER pin is multiplexed with the
EBUA_EBA7 pin.
COL
Collision
COL is an input that indicates that a collision has been
detected on the network medium.
Note: The COL pin is multiplexed with the EBDA15
pin.
CRS
Carrier Sense
CRS is an input that indicates that a non-idle medium,
due either to transmit or receive activity, has been de-
tected.
Note: The CRS pin is multiplexed with the EBDA14
pin.
RX_ER
Receive Error
RX_ER is an input that indicates that the MII trans-
ceiver device has detected a coding error in the receive
frame currently being transferred on the RXD[3:0] pins.
When RX_ER is asserted while RX_DV is asserted, a
CRC error will be indicated in the receive descriptor for
the incoming receive frame. RX_ER is ignored while
RX_DV is deasserted. Special code groups generated
on RXD while RX_DV is deasserted are ignored (e.g.,
Bad SSD in TX and IDLE in T4). RX_ER transitions are
synchronous to RX_CLK rising edges.
Note: The RX_ER pin is multiplexed with the EBD6
pin.
MDC
Management Data Clock
MDC is a non-continuous clock output that provides a
timing reference for bits on the MDIO pin. During MII
management port operations, MDC runs at a nominal
frequency of 2.5 MHz. When no management opera-
tions are in progress, MDC is driven LOW. The MDC is
derived from the Time Base Clock.
If the MII port is not selected, the MDC pin can be left
floating.
Note: The
EBUA_EBD5 pin.
MDIO
Management Data I/O
MDIO is the bidirectional MII management port data
pin. MDIO is an output during the header portion of the
management frame transfers and during the data por-
tions of write transfers. MDIO is an input during the
MDC
pin
is
multiplexed
Input/Output
P R E L I M I N A R Y
with
Am79C973/Am79C975
Output
Input
Input
Input
the
data portions of read data transfers. When an operation
is not in progress on the management port, MDIO is not
dr iven. MDIO transitions from the Am79C973/
Am79C975 controller are synchronous to MDC falling
edges.
If the PHY is attached through an MII physical connec-
tor, then the MDIO pin should be externally pulled down
to V
board, then the MDIO pin should be externally pulled
up to V
Note: The MDIO pin is multiplexed with the EBDA13
pin.
PHY_RST
Physical Layer Reset
PHY_RST is an output pin that is used to reset an ex-
ternal PHY. This output eliminates the need for a fan
out buffer for the PCI RST signal, provides polarity for
the specific external PHY used, and prevents the reset-
ting of the external PHY when the PG input is LOW.
The output polarity is determined by RST_POL bit
(CSR 116, bit 0).
Note: The PHY_RST pin is multiplexed with the
EBUA_EBA6 pin.
RX_CLK
Receive Clock
RX_CLK is a clock input that provides the timing refer-
ence for the transfer of the RX_DV, RXD[3:0], and
RX_ER signals into the Am79C973/Am79C975 device.
RX_CLK must provide a nibble rate clock (25% of the
network data rate). Hence, when the Am79C973/
Am79C975 device is operating at 10 Mbps, it provides
an RX_CLK frequency of 2.5 MHz, and at 100 Mbps it
provides an RX_CLK frequency of 25 MHz.
Note: The RX_CLK pin is multiplexed with the EBD5
pin.
RXD[3:0]
Receive Data
RXD[3:0] is the nibble-wide MII-compatible receive
data bus. Data on RXD[3:0] is sampled on every rising
edge of RX_CLK while RX_DV is asserted. RXD[3:0] is
ignored while RX_DV is de-asserted.
Note: The RXD[3:0] pin is multiplexed with the
EBD[3:0] pins.
RX_DV
Receive Data Valid
RX_DV is an input used to indicate that valid received
data is being presented on the RXD[3:0] pins and
RX_CLK is synchronous to the receive data. In order
for a frame to be fully received by the Am79C973/
Am79C975 device, RX_DV must be asserted prior to
the RX_CLK rising edge, when the first nibble of the
SS
CC
with a 10-k
with a 10-k
5% resistor. If the PHY is on
5% resistor
Output
Input
Input
Input
35