AM79C973BKC\W AMD (ADVANCED MICRO DEVICES), AM79C973BKC\W Datasheet - Page 260

• Manufacturer Part Number: AM79C973BKC\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC\W

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3/3.135V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Not Compliant

SMIU Command Register (MReg Address 31)
Bit No. Name and Description
7
6
5
4
3
2
260
MIRQEN
Default: 0
MIRQEN allows the MIRQ pin to be active if
the interrupt flag MIRQ in the SMIU Interrupt
register is set. If MIRQEN is cleared to 0, the
MIRQ pin will be disabled regardless of the
state of MIRQ. MRIRQEN is cleared by
H_RESET.
MTX_DONEM
Default: 0
If MTX_DONEM is set to a 1, the MTX_DONE
bit in the SMIU Interrupt register will be
masked and unable to set the MIRQ bit.
MTX_DONEM is cleared by H_RESET.
MRX_DONEM
Default: 0
If MRX_DONEM is set to a 1, the MRX_DONE
bit in the SMIU Interrupt register will be
masked and unable to set the MIRQ bit.
MRX_DONEM is cleared by H_RESET.
RESERVED
Default: 0
Reserved bit. For future use only
MLOOP
Default: 0
If MLOOP is set to 0, transmit frames will be
blocked from being received back, in case the
transceiver loops back the data. Setting
MLOOP to 1 enables loopback mode. All data
that is transmitted will be received back, if the
transceiver loop backs the data and the data
passes the acknowledgment frame filter. The
transceiver loopback can be achieved by pro-
gramming the device into loopback mode or by
using an external loopback connector. MLOOP
has no effect., when the Am79C975 controller
is configured for full-duplex operation. Re-
ceives are never blocked in full-duplex mode.
MLOOP is cleared by H_RESET.
MRX_RPA
Default: 0
Read/Write
Read/Write
Read/Write
Read/Write as ZERO only
Read/Write
Read/Write
P R E L I M I N A R Y
Am79C973/Am79C975
1:0
SMIU Interrupt Register (MReg Address 32)
Bit No. Name and Description
7
6
5
4:0
When MRX_RPA is set to a 1, the Am79C975
controller will accept runt frames (frames
shorter than 64 bytes) that pass the acknowl-
edgment frame filter. MRX_RPA is cleared by
H_RESET.
RESERVED
Default: 00 Read/Write as ZERO only
Reserved bits. For future use only
MIRQ
Default: 0
MIRQ indicates that one of the following inter-
rupt
MTX_DONE or MRX_DONE and the associat-
ed mask bit is programmed to allow the event
to cause an interrupt. If the MIRQEN bit in the
SMIU Command register is set to 1 and MIRQ
is set, the MIRQ pin will be active. MIRQ is
cleared by clearing all the active individual in-
terrupt bits that have not been masked out, i.e.
MIRQ will clear after reading the Interrupt reg-
ister. MIRQ is also cleared by H_RESET.
MTX_DONE
Default: 0
MTX_DONE is set by the Am79C975 control-
ler after an alert frame has been transmitted.
When MTX_DONE is set, the MIRQ pin is as-
serted if MIRQEN is set to a 1 and the mask bit
MTX_DONEM in the SMIU Command register
is 0. MTIRQ is automatically cleared after
reading the Interrupt register. MTX_DONE is
also cleared by H_RESET.
MRX_DONE
Default: 0
MRX_DONE is set by the Am79C975 control-
ler after an acknowledgment frame has been
received. When MRX_DONE is set, the MIRQ
pin is asserted if MIRQEN is set to a 1 and the
mask bit MRX_DONEM in the SMIU Com-
mand register is 0. MRX_DONE is automati-
cally cleared after reading the Interrupt
register. MRX_DONE is also cleared by
H_RESET.
RESERVED
causing
Read clear, write has no effect.
Read clear, write has no effect.
Read clear, write has no effect.
conditions
has
occurred: