AM79C973BKC\W AMD (ADVANCED MICRO DEVICES), AM79C973BKC\W Datasheet - Page 178

• Manufacturer Part Number: AM79C973BKC\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC\W

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3/3.135V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Not Compliant

BCR20: Software Style
This register is an alias of the location CSR58. Accesses
to and from this register are equivalent to accesses to
CSR58.
Bit
31-16 RES
15-11 RES
10
178
0
APERREN
EDI/EDO
Name
while EEN = 1, then setup and
hold times of the EEDI pin value
with respect to the EESK signal
edge are not guaranteed.
Reserved locations. Written as
zeros and read as undefined.
Reserved locations. Written as
zeros and read as undefined.
Advanced Parity Error Handling
Enable. When APERREN is set
to 1, the BPE bits (RMD1 and
TMD1, bit 23) start having a
meaning. BPE will be set in the
descriptor associated with the
buffer that was accessed when a
data parity error occurred. Note
ESK has no effect on the EESK
pin unless the PREAD bit is set to
0 and the EEN bit is set to 1.
Read accessible always, write
accessible only when either the
STOP or the SPND bit is set. ESK
is reset to 1 by H_RESET and is
not affected by S_RESET or
STOP.
Data Out. Data that is written to
this bit will appear on the EEDI
output of the interface, except
when the PREAD bit is set to 1 or
the EEN bit is set to 0. Data that
is read from this bit reflects the
value of the EEDO input of the in-
terface.
EDI/EDO has no effect on the
EEDI pin unless the PREAD bit is
set to 0 and the EEN bit is set to
1.
Read accessible always; write
accessible only when either the
STOP or the SPND bit is set. EDI/
EDO is reset to 0 by H_RESET
and is not affected by S_RESET
or STOP.
EEPROM
Description
Data
In/EEPROM
P R E L I M I N A R Y
Am79C973/Am79C975
9
8
RES
SSIZE32
Software Size 32 bits. When set,
that since the advanced parity er-
ror handling uses an additional bit
in the descriptor, SWSTYLE (bits
7-0 of this register) must be set to
2 or 3 to program the Am79C973/
Am79C975 controller to use 32-
bit software structures.
APERREN does not affect the re-
porting of address parity errors or
data parity errors that occur when
the Am79C973/Am79C975 con-
troller is the target of the transfer.
Read anytime; write accessible
only when either the STOP or the
SPND bit is set. APERREN is
cleared by H_RESET and is not
affected by S_RESET or STOP.
Reserved locations. Written as
zeros; read as undefined.
this
Am79C973/Am79C975 controller
utilizes 32-bit software structures
for the initialization block and the
transmit and receive descriptor
entries. When cleared, this bit in-
dicates
Am79C975 controller utilizes 16-
bit software structures for the ini-
tialization block and the transmit
and receive descriptor entries. In
this
Am79C975 controller is back-
wards
Am7990 LANCE and Am79C960
PCnet-ISA controllers.
The value of SSIZE32 is deter-
mined
Am79C975 controller according
to the setting of the Software
Style (SWSTYLE, bits 7-0 of this
register).
Read
SSIZE32 is read only; write oper-
ations will be ignored. SSIZE32
will be cleared after H_RESET
(since SWSTYLE defaults to 0)
and is not affected by S_RESET
or STOP.
If SSIZE32 is reset, then bits
IADR[31:24] of CSR2 will be
used to generate values for the
bit
mode,
compatible
by
that
accessible
indicates
the
the
the
Am79C973/
Am79C973/
Am79C973/
with
that
always.
the
the