AM79C973BKC\W AMD (ADVANCED MICRO DEVICES), AM79C973BKC\W Datasheet - Page 94
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AM79C973BKC\W
Manufacturer Part Number
AM79C973BKC\W
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.AM79C973BKCW.pdf
(304 pages)
Specifications of AM79C973BKC\W
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3/3.135V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
160
Lead Free Status / RoHS Status
Not Compliant
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The EROMCS is driven low for the value ROMTMG +
1. Figure 44 assumes that ROMTMG is set to nine.
EBD[7:0] is sampled with the next rising edge of CLK
ten clock cycles after EBUA_EBA[7:0] was driven with
a new address value. This PCI slave access to the
Flash/EPROM will result in a retry for the very first ac-
cess. Subsequent accesses may give a retry or not, de-
pending on whether or not the data is present and valid.
The access time is dependent on the ROMTMG bits
(BCR18, bits 15-12) and the Flash/EPROM. This ac-
cess mechanism differs from the Expansion ROM ac-
cess mechanism since only one byte is read in this
manner, instead of the 4 bytes in an Expansion ROM
access. The PCI bus will not be held during accesses
through the Expansion Bus Data Port. If the LAAINC
(BCR29, bit 15) is set, the EBADDRL address will be
94
EBUA_EBA [7:0]
Latched Address
EBDA [15:8]
EROMCS
AS_EBO
DEVSEL
FRAME
TRDY
IRDY
EBD
CLK
EBUA_EBA[7:0]
EBDA[15:8]
AS_EBOE
EROMCS
5
EBD[7:0]
Figure 44. Flash Read from Expansion Bus Data Port
CLK
10
Figure 43. Expansion ROM Bus Read Sequence
A[19:16]
15
P R E L I M I N A R Y
EBUA[19:16]
20
Am79C973/Am79C975
1
A[7:2], 0, 0
2
25
3
4
30
incremented and a continuous series of reads from the
Expansion Data Port (EBDATA, BCR30) is possible.
The address incrementor will roll over without warning
and without incrementing the upper address EBAD-
DRU.
The Flash write is almost the same procedure as the
read access, except that the Am79C973/Am79C975
controller will not drive AS_EBOE low. The EROMCS
and EBWE are driven low for the value ROMTMG
again. The write to the FLASH port is a posted write
and will not result in a retry to the PCI unless the host
tries to write a new value before the previous write is
complete, then the host will experience a retry. See Fig-
ure 45.
A[7:2], 0, 1
5
6
35
7
EBDA[15:8]
EBA[7:0]
40
8
A[7:2], 1, 0
9
45
10
11
50
12 13
55
A[7:2], 1, 1
60
21510D-48
21510D-49
66
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