AM79C973BKC\W AMD (ADVANCED MICRO DEVICES), AM79C973BKC\W Datasheet - Page 64

• Manufacturer Part Number: AM79C973BKC\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC\W

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3/3.135V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Not Compliant

Re-initialization may be done via the initialization block
or by setting the STOP bit in CSR0, followed by writing
to CSR15, and then setting the START bit in CSR0.
Note that this form of restart will not perform the same
in the Am79C973/Am79C975 controller as in the C-
LANCE device. In par ticular, upon restar t, the
Am79C973/Am79C975 controller reloads the transmit
and receive descriptor pointers with their respective
base addresses. This means that the software must
clear the descriptor OWN bits and reset its descriptor
ring pointers before restar ting the Am79C973/
Am79C975 controller. The reload of descriptor base
addresses is performed in the C-LANCE device only
after initialization, so that a restart of the C-LANCE
without initialization leaves the C-LANCE pointing at
the same descriptor locations as before the restart.
Suspend
The Am79C973/Am79C975 controller offers two sus-
pend modes that allow easy updating of the CSR reg-
isters without going through a full re-initialization of the
device. The suspend modes also allow stopping the
device with orderly termination of all network activity.
The host requests the Am79C973/Am79C975 control-
ler to enter the suspend mode by setting SPND (CSR5,
bit 0) to 1. The host must poll SPND until it reads back
1 to determine that the Am79C973/Am79C975 control-
ler has entered the suspend mode. When the host sets
SPND to 1, the procedure taken by the Am79C973/
Am79C975 controller to enter the suspend mode de-
pends on the setting of the fast suspend enable bit
(FASTSPND, CSR7, bit 15).
When a fast suspend is requested (FASTSPND is set
to 1), the Am79C973/Am79C975 controller performs a
quick entry into the suspend mode. At the time the
SPND bit is set, the Am79C973/Am79C975 controller
will continue the DMA process of any transmit and/or
receive packets that have already begun DMA activity
until the network activity has been completed. In addi-
tion, any transmit packet that had started transmission
will be fully transmitted and any receive packet that had
begun reception will be fully received. However, no ad-
ditional packets will be transmitted or received and no
additional transmit or receive DMA activity will begin
after networ k activity has ceased. Hence, the
Am79C973/Am79C975 controller may enter the sus-
pend mode with transmit and/or receive packets still in
the FIFOs or the SRAM. This offers a worst case sus-
pend time of a maximum length packet over the possi-
bility of completely emptying the SRAM. Care must be
exercised in this mode, because the entire memory
subsystem of the Am79C973/Am79C975 controller is
suspended. Any changes to either the descriptor rings
or the SRAM can cause the Am79C973/Am79C975
controller to start up in an unknown condition and could
cause data corruption.
64
P R E L I M I N A R Y
Am79C973/Am79C975
When FASTSPNDE is 0 and the SPND bit is set, the
Am79C973/Am79C975 controller may take longer be-
fore entering the suspend mode. At the time the SPND
bit is set, the Am79C973/Am79C975 controller will
complete the DMA process of a transmit packet if it had
already begun and the Am79C973/Am79C975 control-
ler will completely receive a receive packet if it had al-
ready begun. The Am79C973/Am79C975 controller
will not receive any new packets after the completion of
the current reception. Additionally, all transmit packets
stored in the transmit FIFOs and the transmit buffer
area in the SRAM (if one is present) will be transmitted,
and all receive packets stored in the receive FIFOs and
the receive buffer area in the SRAM (if selected) will be
transferred into system memory. Since the FIFO and
the SRAM contents are flushed, it may take much
longer before the Am79C973/Am79C975 controller en-
ters the suspend mode. The amount of time that it
takes depends on many factors including the size of the
SRAM, bus latency, and network traffic level.
Upon completion of the described operations, the
Am79C973/Am79C975 controller sets the read-version
of SPND to 1 and enters the suspend mode. In sus-
pend mode, all of the CSR and BCR registers are ac-
cessible. As long as the Am79C973/Am79C975
controller is not reset while in suspend mode (by
H_RESET, S_RESET, or by setting the STOP bit), no
re-initialization of the device is required after the device
comes out of suspend mode. When SPND is set to 0,
the Am79C973/Am79C975 controller will leave the
suspend mode and will continue at the transmit and re-
ceive descriptor ring locations where it was when it en-
tered the suspend mode.
See the section on Magic Packet™ technology for de-
tails on how that affects suspension of the Am79C973/
Am79C975 controller.
Buffer Management
Buffer management is accomplished through message
descriptor entries organized as ring structures in mem-
ory. There are two descriptor rings, one for transmit and
one for receive. Each descriptor describes a single
buffer. A frame may occupy one or more buffers. If mul-
tiple buffers are used, this is referred to as buffer chain-
ing.
Descriptor Rings
Each descriptor ring must occupy a contiguous area of
memory. During initialization, the user-defined base
address for the transmit and receive descriptor rings,
as well as the number of entries contained in the de-
scriptor rings are set up. The programming of the soft-
ware style (SWSTYLE, BCR20, bits 7-0) affects the
way the descriptor rings and their entries are arranged.
When SWSTYLE is at its default value of 0, the de-
scriptor rings are backwards compatible with the
Am79C90 C-LANCE and the Am79C96x PCnet-ISA