AM79C973BKC\W AMD (ADVANCED MICRO DEVICES), AM79C973BKC\W Datasheet - Page 62

• Manufacturer Part Number: AM79C973BKC\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC\W

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3/3.135V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Not Compliant

Burst FIFO DMA Transfers
Bursting is only perfor med by the Am79C973/
Am79C975 controller if the BREADE and/or BWRITE
bits of BCR18 are set. These bits individually enable/
disable the ability of the Am79C973/Am79C975 con-
troller to perform burst accesses during master read
operations and master write operations, respectively.
A burst transaction will start with an address phase, fol-
lowed by one or more data phases. AD[1:0] will always
be 0 during the address phase indicating a linear burst
order.
During FIFO DMA read operations, all byte lanes will
always be active. The Am79C973/Am79C975 control-
ler will internally discard unused bytes. During the first
and the last data phases of a FIFO DMA burst write op-
eration, one or more of the byte enable signals may be
inactive. All other data phases will always write a com-
plete DWord.
Figure 29 shows the beginning of a FIFO DMA write
with the beginning of the buffer not aligned to a DWord
boundary. The Am79C973/Am79C975 controller starts
off by writing only three bytes during the first data
phase. This operation aligns the address for all other
data transfers to a 32-bit boundar y so that the
Am79C973/Am79C975 controller can continue burst-
ing full DWords.
If a receive buffer does not end on a DWord boundary,
the Am79C973/Am79C975 controller will perform a
non-DWord write on the last transfer to the buffer. Fig-
ure 30 shows the final three FIFO DMA transfers to a
receive buffer. Since there were only nine bytes of
space left in the receive buffer, the Am79C973/
Am79C975 controller bursts three data phases. The
first two data phases write a full DWord, the last one
only writes a single byte.
Note that the Am79C973/Am79C975 controller will al-
ways perform a DWord transfer as long as it owns the
buffer space, even when there are less than four bytes
to write. For example, if there is only one byte left for the
current receive frame, the Am79C973/Am79C975 con-
troller will write a full DWord, containing the last byte of
the receive frame in the least significant byte position
(BSWP is cleared to 0, CSR3, bit 2). The content of the
other three bytes is undefined. The message byte
62
P R E L I M I N A R Y
Am79C973/Am79C975
count in the receive descriptor always reflects the exact
length of the received frame.
The Am79C973/Am79C975 controller will continue
transferring FIFO data until the transmit FIFO is filled to
its high threshold (read transfers) or the receive FIFO
is emptied to its low threshold (write transfers), or the
Am79C973/Am79C975 controller is preempted, and
the PCI Latency Timer is expired. The host should use
the values in the PCI MIN_GNT and MAX_LAT regis-
ters to determine the value for the PCI Latency Timer.
Figure 29. FIFO Burst Write At Start Of Unaligned
DEVSEL
FRAME
TRDY
IRDY
C/BE
REQ
GNT
PAR
CLK
AD
1
DEVSEL is sampled
2
Buffer
0111
ADD
3
DATA
0001
PAR
4
DATA
PAR
5
0000
21510D-34
DATA
PAR
6