AM79C973BKC\W AMD (ADVANCED MICRO DEVICES), AM79C973BKC\W Datasheet - Page 98

• Manufacturer Part Number: AM79C973BKC\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC\W

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3/3.135V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Not Compliant

EEPROM Interface
The Am79C973/Am79C975 controller contains a built-
in capability for reading and writing to an external serial
93C46 EEPROM. This built-in capability consists of an
interface for direct connection to a 93C46 compatible
EEPROM, an automatic EEPROM read feature, and a
user-programmable register that allows direct access
to the interface pins.
Automatic EEPROM Read Operation
Shortly after the deassertion of the RST pin, the
Am79C973/Am79C975 controller will read the con-
tents of the EEPROM that is attached to the interface.
Because of this automatic-read capability of the
Am79C973/Am79C975 controller, an EEPROM can be
us ed t o pr ogram m any of th e feat ur es of th e
Am79C973/Am79C975 controller at power-up, allow-
ing system-dependent configuration information to be
stored in the hardware, instead of inside the device
driver.
If an EEPROM exists on the interface, the Am79C973/
Am79C975 controller will read the EEPROM contents
at the end of the H_RESET operation. The EEPROM
contents will be serially shifted into a temporary regis-
ter and then sent to various register locations on board
the Am79C973/Am79C975 controller. Access to the
Am79C973/Am79C975 configuration space, the Ex-
pansion ROM or any I/O resource is not possible during
the EEPROM read operation. The Am79C973/
Am79C975 controller will terminate any access at-
tempt with the assertion of DEVSEL and STOP while
TRDY is not asserted, signaling to the initiator to dis-
connect and retry the access at a later time.
A checksum verification is performed on the data that
is read from the EEPROM. If the checksum verification
passes, PVALID (BCR19, bit 15) will be set to 1. If the
checksum verification of the EEPROM data fails,
PVALID will be cleared to 0, and the Am79C973/
Am79C975 controller will force all EEPROM-program-
mable BCR registers back to their H_RESET default
values. However, the content of the Address PROM lo-
cations (offsets 0h - Fh from the I/O or memory
mapped I/O base address) will not be cleared. The 8-
bit checksum for the entire 68 bytes of the EEPROM
should be FFh.
If no EEPROM is present at the time of the automatic
read operation, the Am79C973/Am79C975 controller
will recognize this condition and will abort the auto-
matic read operation and clear both the PREAD and
PVALID bits in BCR19. All EEPROM-programmable
BCR registers will be assigned their default values after
H_RESET. The content of the Address PROM loca-
tions (offsets 0h - Fh from the I/O or memory mapped
I/O base address) will be undefined.
98
P R E L I M I N A R Y
Am79C973/Am79C975
EEPROM Auto-Detection
The Am79C973/Am79C975 controller uses the EESK/
LED1/SFBD pin to determine if an EEPROM is present
in the system. At the rising edge of CLK during the last
clock during which RST is asserted, the Am79C973/
Am79C975 controller will sample the value of the
EESK/LED1/SFBD pin. If the sampled value is a 1,
then the Am79C973/Am79C975 controller assumes
that an EEPROM is present, and the EEPROM read
operation begins shortly after the RST pin is deas-
serted. If the sampled value of EESK/LED1/SFBD is a
0, the Am79C973/Am79C975 controller assumes that
an external pulldown device is holding the EESK/LED1/
SFBD pin low, indicating that there is no EEPROM in
the system. Note that if the designer creates a system
that contains an LED circuit on the EESK/LED1/SFBD
pin, but has no EEPROM present, then the EEPROM
auto-detection function will incorrectly conclude that an
EEPROM is present in the system. However, this will
not pose a problem for the Am79C973/Am79C975 con-
troller, since the checksum verification will fail.
Direct Access to the Interface
The user may directly access the port through the
EEPROM register, BCR19. This register contains bits
that can be used to control the interface pins. By per-
forming an appropriate sequence of accesses to
BCR19, the user can effectively write to and read from
the EEPROM. This feature may be used by a system
configuration utility to program hardware configuration
information into the EEPROM.
EEPROM-Programmable Registers
The following registers contain configuration informa-
tion that will be programmed automatically during the
EEPROM read operation:
I/O offsets 0h-Fh Address PROM locations
BCR2
BCR4
BCR5
BCR6
BCR7
BCR9
BCR18
BCR22
BCR23
BCR24
BCR25
BCR26
BCR27
BCR32
BCR33
Miscellaneous Configuration
LED0 Status
LED1 Status
LED2 Status
LED3 Status
Full-Duplex Control
Burst and Bus Control
PCI Latency
PCI Subsystem Vendor ID
PCI Subsystem ID
SRAM Size
SRAM Boundary
SRAM Interface Control
PHY Control and Status
PHY Address