AM79C973BKC\W AMD (ADVANCED MICRO DEVICES), AM79C973BKC\W Datasheet - Page 204

• Manufacturer Part Number: AM79C973BKC\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC\W

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3/3.135V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Not Compliant

RLEN and TLEN
When SSIZE32 (BCR20, bit 8) is set to 0, the software
structures are defined to be 16 bits wide, and the RLEN
and TLEN fields in the initialization block are each three
bits wide. The values in these fields determine the num-
ber of transmit and receive Descriptor Ring Entries
(DRE) which are used in the descriptor rings. Their
meaning is shown in Table 56. If a value other than those
listed in Table 56 is desired, CSR76 and CSR78 can be
written after initialization is complete.
When SSIZE32 (BCR20, bit 8) is set to 1, the software
structures are defined to be 32 bits wide, and the RLEN
and TLEN fields in the initialization block are each 4 bits
wide. The values in these fields determine the number
of transmit and receive Descriptor Ring Entries (DRE)
which are used in the descriptor rings. Their meaning
is shown in Table 57.
If a value other than those listed in Table 57 is desired,
CSR76 and CSR78 can be written after initialization is
complete.
RDRA and TDRA
RDRA and TDRA indicate where the transmit and re-
ceive descriptor rings begin. Each DRE must be located
at a 16-byte address boundary when SSIZE32 is set to
1 (BCR20, bit 8). Each DRE must be located at an 8-
204
IADR+0Ch
IADR+00h
IADR+04h
IADR+08h
IADR+10h
IADR+14h
IADR+18h
Address
Table 56. R/TLEN Decoding (SSIZE32 = 0)
R/TLEN
000
001
010
011
100
101
110
111
31-28
TLEN
Bits
27-24
RES
Bits
Number of DREs
Table 55. Initialization Block (SSIZE32 = 1)
RES
128
16
32
64
1
2
4
8
RLEN
23-20
P R E L I M I N A R Y
Bits
Am79C973/Am79C975
19-16
RES
Bits
LADRF 31-00
LADRF 63-32
RDRA 31-00
TDRA 31-00
PADR 31-00
byte address boundary when SSIZE32 is set to 0
(BCR20, bit 8).
LADRF
The Logical Address Filter (LADRF) is a 64-bit mask
that is used to accept incoming Logical Addresses. If
the first bit in the incoming address (as transmitted on
the wire) is a 1, it indicates a logical address. If the first
bit is a 0, it is a physical address and is compared
against the physical address that was loaded through
the initialization block.
A logical address is passed through the CRC generator,
producing a 32-bit result. The high order 6 bits of the
CRC is used to select one of the 64 bit positions in the
Logical Address Filter. If the selected filter bit is set, the
address is accepted and the frame is placed into mem-
ory.
The Logical Address Filter is used in multicast address-
ing schemes. The acceptance of the incoming frame
based on the filter value indicates that the message may
be intended for the node. It is the node’s responsibility
to determine if the message is actually intended for the
node by comparing the destination address of the stored
message with a list of acceptable logical addresses.
Table 57. R/TLEN Decoding (SSIZE32 = 1)
15-12
Bits
R/TLEN
11XX
1X1X
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
11-8
Bits
PADR 47-32
MODE
Number of DREs
Bits
7-4
128
256
512
512
512
16
32
64
1
2
4
8
Bits
3-0