AM79C973BKC\W AMD (ADVANCED MICRO DEVICES), AM79C973BKC\W Datasheet - Page 150

• Manufacturer Part Number: AM79C973BKC\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC\W

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3/3.135V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Not Compliant

CSR80: DMA Transfer Counter and FIFO Threshold
Control
Bit
31-16 RES
15-14 RES
13-12 RCVFW[1:0] Receive
150
Name
Reserved locations. Written as
zeros and read as undefined.
Reserved locations. Written as
zeros and read as undefined.
RCVFW controls the point at
which receive DMA is requested
in relation to the number of re-
ceived bytes in the Receive FIFO.
RCVFW specifies the number of
bytes which must be present
(once the frame has been verified
as a non-runt) before receive
DMA is requested. Note however
that, if the network interface is op-
erating in half-duplex mode, in or-
der for receive DMA to be
performed for a new frame, at
least 64 bytes must have been re-
ceived. This effectively avoids
having to react to receive frames
which are runts or suffer a colli-
sion during the slot time (512 bit
times). If the Runt Packet Accept
feature is enabled or if the net-
work interface is operating in full-
duplex mode, receive DMA will
be requested as soon as either
the RCVFW threshold is reached,
or a complete valid receive frame
is detected (regardless of length).
When the FDRPAD (BCR9, bit 2)
is
Am79C975 controller is in full-du-
plex mode, in order for receive
DMA to be performed for a new
frame, at least 64 bytes must
have been received. This effec-
tively disables the runt packet ac-
cept feature in full duplex.
by H_RESET, S_RESET, or
STOP.
When operating in the NO-SRAM
mode (no SRAM enabled), the
Bus Receive FIFO and the MAC
Receive operate like a single
FIFO and the watermark value
selected by RCVFW[1:0] sets the
number of bytes that must be
Description
set
and
FIFO
the
Am79C973/
Watermark.
P R E L I M I N A R Y
Am79C973/Am79C975
11-10 XMTSP[1:0] Transmit Start Point. XMTSP
Table 26. Receive Watermark Programming
RCVFW[1:0]
00
01
10
11
present in the FIFO before re-
ceive DMA is requested.
When operating with the SRAM,
the Bus Receive FIFO, and the
MAC Receive FIFO operate inde-
pendently on the bus side and
MAC side of the SRAM, respec-
tively. In this case, the watermark
value set by RCVFW[1:0] sets the
number of bytes that must be
present in the Bus Receive FIFO
only. See Table 26.
Read/Write accessible only when
either the STOP or the SPND bit
is set. RCVFW[1:0] is set to a val-
ue of 01b (64 bytes) after
H_RESET or S_RESET and is
unaffected by STOP.
controls the point at which pream-
ble transmission attempts to com-
mence in relation to the number
of bytes written to the MAC
Transmit FIFO for the current
transmit frame. When the entire
frame is in the MAC Transmit
FIFO, transmission will start re-
gardless of the value in XMTSP.
If the network interface is operat-
ing in half-duplex mode, regard-
less of XMTSP, the FIFO will not
internally overwrite its data until
at least 64 bytes (or the entire
frame if shorter than 64 bytes)
have been transmitted onto the
network. This ensures that for
collisions within the slot time win-
dow, transmit data need not be
rewritten to the Transmit FIFO,
and retries will be handled auton-
omously by the MAC. If the Dis-
able Retry feature is enabled, or if
the network is operating in full-du-
plex
Am79C975 controller can over-
write the beginning of the frame
as soon as the data is transmit-
mode,
Bytes Received
Reserved
112
16
64
the
Am79C973/