AM79C973BKC\W AMD (ADVANCED MICRO DEVICES), AM79C973BKC\W Datasheet - Page 68

• Manufacturer Part Number: AM79C973BKC\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC\W

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3/3.135V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Not Compliant

the OWN bit of this descriptor, the Am79C973/
Am79C975 controller will again immediately request
the bus in order to access the next TDTE location in the
ring.
If the OWN bit is set and the buffer length is 0, the OWN
bit will be cleared. In the C-LANCE device, the buffer
length of 0 is interpreted as a 4096-byte buffer. A zero
length buffer is acceptable as long as it is not the last
buffer in a chain (STP = 0 and ENP = 1).
If the OWN bit and STP are set, then microcode control
proceeds to a routine that will enable transmit data
transfers to the FIFO. The Am79C973/Am79C975 con-
troller will look ahead to the next transmit descriptor
after it has performed at least one transmit data trans-
fer from the first buffer.
If the Am79C973/Am79C975 controller does not own
the next TDTE (i.e., the second TDTE for this frame), it
will complete transmission of the current buffer and up-
date the status of the current (first) TDTE with the
BUFF and UFLO bits being set. If DXSUFLO (CSR3,
bit 6) is cleared to 0, the underflow error will cause the
transmitter to be disabled (CSR0, TXON = 0). The
Am79C973/Am79C975 controller will have to be re-ini-
tialized to restore the transmit function. Setting DXSU-
FLO to 1 enables the Am79C973/Am79C975 controller
to gracefully recover from an underflow error. The de-
vice will scan the transmit descriptor ring until it finds ei-
ther the start of a new frame or a TDTE it does not own.
To avoid an underflow situation in a chained buffer
transmission, the system should always set the trans-
mit chain descriptor own bits in reverse order.
If the Am79C973/Am79C975 controller does own the
second TDTE in a chain, it will gradually empty the con-
tents of the first buffer (as the bytes are needed by the
transmit operation), perform a single-cycle DMA trans-
fer to update the status of the first descriptor (clear the
OWN bit in TMD1), and then it may perform one data
DMA access on the second buffer in the chain before
executing another lookahead operation. (i.e., a looka-
head to the third descriptor.)
It is imperative that the host system never reads the
TDTE OWN bits out of order. The Am79C973/
Am79C975 controller normally clears OWN bits in strict
FIFO order. However, the Am79C973/Am79C975 con-
troller can queue up to two frames in the transmit FIFO.
When the second frame uses buffer chaining, the
Am79C973/Am79C975 controller might return owner-
ship out of normal FIFO order. The OWN bit for last
(and maybe only) buffer of the first frame is not cleared
until transmission is completed. During the transmis-
sion the Am79C973/Am79C975 controller will read in
buffers for the next frame and clear their OWN bits for
all but the last one. The first and all intermediate buffers
of the second frame can have their OWN bits cleared
68
P R E L I M I N A R Y
Am79C973/Am79C975
before the Am79C973/Am79C975 controller returns
ownership for the last buffer of the first frame.
If an error occurs in the transmission before all of the
bytes of the current buffer have been transferred, trans-
mit status of the current buffer will be immediately up-
dated. If the buffer does not contain the end of packet,
the Am79C973/Am79C975 controller will skip over the
rest of the frame which experienced the error. This is
done by returning to the polling microcode where the
Am79C973/Am79C975 controller will clear the OWN
bit for all descriptors with OWN = 1 and STP = 0 and
continue in like manner until a descriptor with OWN = 0
(no more transmit frames in the ring) or OWN = 1 and
STP = 1 (the first buffer of a new frame) is reached.
At the end of any transmit operation, whether success-
ful or with errors, immediately following the completion
of the descriptor updates, the Am79C973/Am79C975
controller will always perform another polling operation.
As described earlier, this polling operation will begin
with a check of the current RDTE, unless the
Am79C973/Am79C975 controller already owns that
descriptor. Then the Am79C973/Am79C975 controller
will poll the next TDTE. If the transmit descriptor OWN
bit has a 0 value, the Am79C973/Am79C975 controller
will resume incrementing the poll time counter. If the
transmit descriptor OWN bit has a value of 1, the
Am79C973/Am79C975 controller will begin filling the
FIFO with transmit data and initiate a transmission.
This end-of-operation poll coupled with the TDTE loo-
kahead operation allows the Am79C973/Am79C975
controller to avoid inserting poll time counts between
successive transmit frames.
By default, whenever the Am79C973/Am79C975 con-
troller completes a transmit frame (either with or with-
out error) and writes the status information to the
current descriptor, then the TINT bit of CSR0 is set to
indicate the completion of a transmission. This causes
an interrupt signal if the IENA bit of CSR0 has been set
and the TINTM bit of CSR3 is cleared. The Am79C973/
Am79C975 controller provides two modes to reduce
the number of transmit interrupts. The interrupt of a
successfully transmitted frame can be suppressed by
setting TINTOKD (CSR5, bit 15) to 1. Another mode,
which is enabled by setting LTINTEN (CSR5, bit 14) to
1, allows suppression of interrupts for successful trans-
missions for all but the last frame in a sequence.
Receive Descriptor Table Entry
If the Am79C973/Am79C975 controller does not own
both the current and the next Receive Descriptor Table
Entry (RDTE), then the Am79C973/Am79C975 con-
troller will continue to poll according to the polling se-
quence described above. If the receive descriptor ring
length is one, then there is no next descriptor to be
polled.