XRT91L31IQTR-F Exar Corporation, XRT91L31IQTR-F Datasheet
XRT91L31IQTR-F
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XRT91L31IQTR-F Summary of contents
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JULY 2008 GENERAL DESCRIPTION The XRT91L31 is a fully integrated SONET/SDH transceiver for SONET/SDH 622.08 Mbps STS-12/ STM-4 or 155.52 Mbps STS-3/STM-1 applications. The transceiver includes an on-chip Clock Multiplier Unit (CMU), which uses a high frequency Phase- Locked Loop ...
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XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER FEATURES • Targeted for SONET STS-12/STS-3 and SDH STM-4/STM-1 Applications • Selectable full duplex operation between STS-12/STM-4 standard rate of 622.08 Mbps or STS-3/STM-1 155.52 Mbps • Single-chip fully integrated solution containing parallel-to-serial converter, ...
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REV. 1.0 QFP P O IGURE THE 49 AGND 50 49 TXPCLK_IO FL1 51 50 TXDI7 STS1_1 52 51 TXDI6 MCLK_1 53 52 GND GND 54 53 TXDI5 RCLK_1 55 54 TXDI4 RPOS_1 56 ...
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XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER GENERAL DESCRIPTION .................................................................................................1 APPLICATIONS ........................................................................................................................................... XRT91L31 ...................................................................................................................................... 1 IGURE LOCK IAGRAM OF ......................................................................................................................................................2 FEATURES QFP P O XRT91L31 (T IGURE THE ...
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REV. 1.0 ABLE LTERNATE RANSMIT ARALLEL ................................................................................................................................................................... 27 3.5 TRANSMIT PARALLEL INPUT TO SERIAL OUTPUT (PISO) ...................................................................... IGURE IMPLIFIED LOCK IAGRAM OF 3.6 CLOCK MULTIPLIER UNIT (CMU) AND RE-TIMER ...
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XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER PIN DESCRIPTIONS PIN DESCRIPTION AME EVEL RESET LVTTL, LVCMOS STS12/STS3 LVTTL, LVCMOS CMUFREQSEL LVTTL, LVCMOS CDR_BW/VDD LVTTL, LVCMOS ABLE ARDWARE ONTROL P YPE Master ...
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REV. 1.0.2 PIN DESCRIPTION AME EVEL CDRREFSEL LVTTL, LVCMOS LOOPTIME LVTTL, LVCMOS CDRDIS LVTTL, LVCMOS STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER P YPE Clock and Data Recover Unit Reference Frequency Select Selects the Clock and ...
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XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER PIN DESCRIPTION AME EVEL PIO_CTRL LVTTL, LVCMOS RLOOPS LVTTL, LVCMOS DLOOP LVTTL, LVCMOS ALOOP LVTTL, LVCMOS P YPE Transmit Parallel Clock Directional Control Transmit Parallel Clock Output Operation ...
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REV. 1.0.2 TRANSMITTER SECTION AME EVEL TXDI0 LVTTL, TXDI1 LVCMOS TXDI2 TXDI3 TXDI4 TXDI5 TXDI6 TXDI7 TXOP LVPECL Diff TXON TXPCLK_IO LVTTL, LVCMOS STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER P YPE Transmit Parallel Data Input ...
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XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER TRANSMITTER SECTION AME EVEL REFCLKP LVPECL Diff REFCLKN TTLREFCLK LVTTL, LVCMOS P YPE Reference Clock Input (77.76 MHz or 19.44 MHz) 17 This differential clock input reference is ...
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REV. 1.0.2 RECEIVER SECTION PIN DESCRIPTION AME EVEL RXDO0 LVTTL, RXDO1 LVCMOS RXDO2 RXDO3 RXDO4 RXDO5 RXDO6 RXDO7 RXIP Diff LVPECL RXIN XRXCLKIP Diff LVPECL XRXCLKIN RXPCLKO LVTTL, LVCMOS CDRAUX- LVTTL, REFCLK LVCMOS OOF LVTTL, LVCMOS STS-12/STM-4 ...
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XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER PIN DESCRIPTION AME EVEL FRAMEPULSE LVTTL, LVCMOS CAP1P Analog CAP2P CAP1N Analog CAP2N DLOSDIS LVTTL, LVCMOS LOSEXT SE-LVPECL POWER AND GROUND PIN DESCRIPTION N T AME YPE VDD3.3 PWR 18, 31, ...
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REV. 1.0.2 PIN DESCRIPTION N T AME YPE VDD_PECL PWR AGND_TX PWR AGND_RX PWR GND GND 21, 28, 35, 45, 46, 52 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 3.3V Input/Output LVPECL Bus Power Supply These pins require ...
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XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 1.0 FUNCTIONAL DESCRIPTION The XRT91L31 transceiver is designed to operate with a SONET Framer/ASIC device and provide a high- speed serial interface to optical networks. The transceiver converts 8-bit parallel data running at 77.76 ...
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STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER REV. 1.0.2 2.0 RECEIVE SECTION The receive section of XRT91L31 include the inputs RXIP/N, followed by the clock and data recovery unit (CDR) and receive serial-to-parallel converter. The receiver accepts the high speed Non-Return to ...
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XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 2.2 Recieve Serial Data Input Timing The received High-Speed Serial Differential Data Input must adhere to the set-up and hold time timing specifications below IGURE ECEIVE IGH PEED ...
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STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER REV. 1.0.2 2.3 Receive Clock and Data Recovery The clock and data recovery (CDR) unit accepts the high speed NRZ serial data from the Differential LVPECL receiver and generates a clock that is the same ...
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XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER differential clock XRXCLKIP/N coming from the optical module or an external clock recovery unit. shows the possible internal paths of the recovered clock and data IGURE NTERNAL LOCK AND ...
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STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER REV. 1.0.2 2.4 External Receive Loop Filter Capacitors These external loop filter 0.47μF non-polarized capacitors provide the necessary components to achieve the required receiver jitter performance. They must be well isolated to prohibit noise entering ...
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XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER Tx output while the LOSEXT input is set to a “LOW” state. Note that the DLOSDIS control pin has no impact on the CDR muting function due to LOSEXT. DLOSDIS only applies to muting ...
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STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER REV. 1.0.2 2.8 Receive Parallel Output Interface The 8-bit Single-Ended LVTTL running at 77.76 Mbps (STS-12/STM-4) or 19.44 Mbps (STS-3/STM-1) parallel data output of the receive path is used to interface to a SONET Framer/ASIC ...
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XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 2.10 Receive Parallel Data Output Timing The receive parallel data output from the STS-12/STM-4 or STS-3/STM-1 receiver will adhere to the setup and hold times shown in Figure 10 ,Table specifications. F 10. R ...
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STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER REV. 1.0.2 T 11: PECL ABLE S YMBOL t PECL output rise time (20% to 80%) R_PECL t PECL output fall time (80% to 20%) F_PECL t TTL output rise time (10% to 90%) R_TTL ...
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XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 3.0 TRANSMIT SECTION The transmit section of the XRT91L31 accepts 8-bit parallel data and converts it to serial Differential LVPECL data output intented to interface to an optical module. It consists of an 8-bit ...
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STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER REV. 1.0.2 3.2 Transmit Parallel Data Input Timing When applying parallel data input to the transmitter, the setup and hold times should be followed as shown in Figure 12, Table 12 and Table 13. F ...
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XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 3.3 Alternate Transmit Parallel Bus Clock Input Option To decouple transmit parallel clock domains of the framer/mapper device and the XRT91L31 transceiver and to eliminate difficult timing issues between them, the transmit parallel clock ...
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STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER REV. 1.0 ABLE LTERNATE RANSMIT S YMBOL t TXPCLK_IO t Transmit data setup time with respect to TXPCLK_IO TXDI_SU t Transmit data hold time with respect to TXPCLK_IO TXDI_HD T 15: ...
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XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 3.6 Clock Multiplier Unit (CMU) and Re-Timer The clock synthesizer uses a 77.76 MHz or a 19.44 MHz reference clock to generate the 622.08 MHz (for STS- 12/STM-4) or 155.52 MHz (for STS-3/STM-1) SONET/SDH ...
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STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER REV. 1.0.2 3.7 Loop Timing and Clock Control Two types of loop timing are possible in the XRT91L31. In the internal loop timing mode, loop timing is controlled by the LOOPTIME pin. This mode is ...
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XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER F 16 IGURE OOP IMING ODE SING REFCLKP REFCLKN TTLREFCLK TXDI[7:0] TXPCLK_IO ENB ENB PIO_CTRL LOOPTIME CDRDIS RXDO[7: Div by 8 RXPCLKO 3.8 Transmit Serial Output Control The ...
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STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER REV. 1.0.2 4.0 DIAGNOSTIC FEATURES 4.1 Serial Remote Loopback The serial remote loopback function is activated by setting RLOOPS "High". When serial remote loopback is activated, the high-speed serial receive data from RXIP/N is presented ...
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XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 4.3 Analog Local Loopback Analog Local Loopback (ALOOP) controls a more comprehensive version of digital local loopback in which the point where the transmit data is looped back is moved all the way back ...
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STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER REV. 1.0.2 4.5 Eye Diagram The XRT91L31 Eye diagram illustrates the transmit serial output signal integrity and quality IGURE RANSMIT LECTRICAL STS-3/STM-1 4.6 SONET Jitter Requirements SONET equipment jitter requirements ...
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XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER F 23. GR-253 J T IGURE ITTER OLERANCE A 3 Input Jitter Amplitude ( OC-N/STS-N LEVEL T 18: XRT91L31 R ABLE F B REQUENCY AND I NTERFACE L ...
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STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER REV. 1.0 IGURE ITTER OLERANCE OR XRT91L31 Jitter Tolerance (OC12) 1000.00 100.00 10.00 1.00 0.10 1E+ IGURE ITTER OLERANCE OR 100.00 10.00 1.00 0.10 1E+00 ...
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XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER The jitter transfer function is a ratio between the jitter output and jitter input for a component, or system often expressed in dB. A negative dB jitter transfer indicates the element removed jitter. A ...
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STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER REV. 1.0.2 T 19: XRT91L31 O ABLE EASUREMENT AND ILTER -3dB F REQUENCIES I NTERFACE IGH ASS OW O (KH ) (MH PTICAL Z OC3/STM1 12 1.3 OC12/STM4 ...
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XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER ABSOLUTE MAXIMUM POWER AND INPUT/OUTPUT RATINGS S T YMBOL YPE LVTTL DC logic signal output voltage LVPECL Input current LVTTL Input current N : Stresses listed under Absolute Maximum Power and I/O ratings may ...
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STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER REV. 1.0.2 LVPECL AND LVTTL LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS E C LECTRICAL HARACTERISTICS Test Conditions: VDD = 3. unless otherwise specified YMBOL YPE ARAMETER V LVPECL Output High Voltage ...
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XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER F 28. D IGURE IFFERENTIAL VOLTAGE SWING DEFINITIONS V(+) V(-) V = V(+)-V(-) DIFF ART UMBER XRT91L31IQ 64-pin Plastic Quad Flat Pack (10.0 x 10.0 x 2.0 mm, QFP) PACKAGE ...
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STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER REV. 1.0.2 Note: The control dimension is in millimeters. SYMBOL α REVISION HISTORY EVISION ATE 1.0.0 October 2007 1.0.1 Feb 2008 1.0.2 July ...