XRT91L31IQTR-F Exar Corporation, XRT91L31IQTR-F Datasheet - Page 19

• Manufacturer Part Number: XRT91L31IQTR-F
• Description: SONET SDH - 8 Bit OC12/STM4, OC3/STM1 PHY Transceiver (with Improved Jitter Transfer Used For Loop Timing Applications)
• Manufacturer: Exar Corporation
• Type: Transceiverr

Specifications of XRT91L31IQTR-F

• Input: LVCMOS, LVPECL, LVTTL
• Output: LVCMOS, LVPECL, LVTTL
• Frequency - Max: 77.76MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.2
These external loop filter 0.47μF non-polarized capacitors provide the necessary components to achieve the
required receiver jitter performance. They must be well isolated to prohibit noise entering the CDR block and
should be placed as close to the pins as much as possible.
loop filter components. These two non-polarized capacitors should be of +/- 10% tolerance.
XRT91L31 supports internal Loss of Signal detection (LOS) and external LOS detection. The internal Loss of
Signal Detector monitors the incoming data stream and if the incoming data stream has no transition
continuously for more than 128 bit periods, Loss of Signal is declared. This LOS detection will be removed
when the circuit detects 16 transitions in a 128 bit period sliding window. Pulling the corresponding DLOSDIS
signal to a high level will disable the internal LOS detection circuit. The external LOS function is supported by
the LOSEXT input. The Single-Ended LVPECL input usually comes from the optical module through an output
usually called “SD” or “FLAG” which indicates the lack or presence of optical power. Depending on the
manufacturer of these devices, the polarity of this signal can be either active "Low" or active "High". LOSEXT is
an active "Low" signal requiring a low level to assert or invoke a forced LOS. The external LOSEXT input pin
and internal LOS detector are gated to control detection and declaration of Loss of Signal (see
Whenever LOS is internally detected or an external LOS is asserted thru the LOSEXT pin, and none of the
local loopback loops is enabled, the XRT91L31 will automatically force the receive parallel data output to a
logic state "0" for the entire duration that a LOS condition is declared. This acts as a receive data mute upon
LOS function to prevent random noise from being misinterpreted as valid incoming data.
loopbacks DLOOP or ALOOP is enabled, then LOS conditions will not mute the RX parallel output.
F
During RLOOPS operation, the 91L31 mutes the RLOOPS data going to Tx output upon detection of DLOS
while DLOSDIS is not enabled. During RLOOPS operation, the 91L31 also mutes the RLOOPS data going to
F
2.4
2.5
IGURE
IGURE
7. LOS D
6. E
External Receive Loop Filter Capacitors
Loss Of Signal
XTERNAL
ECLARATION
pin 39
DLOS (internal signal)
L
CAP1P
OOP
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
LOSEXT
DLOSDIS
F
ILTERS
non-polarized
C
0.47uF
IRCUIT
CAP2P
pin 42
ALOOP
DLOOP
19
pin 40
RLOOPS
CAP1N
Figure 6
non-polarized
0.47uF
‘0’ = No LOS detection:
mute receive parallel data bus
‘1’ = LOS_detection:
receive parallel data bus
‘0’ = No LOS detection:
Do not mute Tx serial data output
‘1’ = LOS_detection:
serial data output
(Internal Signal)
shows the pin connections and external
RLPS_D_MUTE
(Internal Signal)
CAP2N
pin 41
Mute
Mute Tx
Do not
When the local
XRT91L31
Figure
7.)